Someone's confused

Paul Koning paulkoning at
Mon Jun 8 19:24:18 CDT 2020

> On Jun 8, 2020, at 6:40 PM, Antonio Carlini via cctalk <cctalk at> wrote:
> On 08/06/2020 21:54, Chuck Guzis via cctalk wrote:
>> Although there are exceptions.  I recall that it was possible, using
>> large page sizes on the CDC STAR-100 to execute an instruction that
>> could never get started.  The STAR had 512KW (64 bits) of memory and a
>> large page size was 64KW.  A typical vector instruction could require 6
>> addresses for source, destination and control vectors.  Put the starting
>> address of any of these in last 8 words of a page and the hardware
>> faulted preemptively for next page.   It was kind of funny to watch; the
>> P-counter for the user never budged, but the pager was sucking up time
>> like crazy.  I think someone eventually devised a check in the pager for
>> this case, but I'm not certain.
> There was a standard VAX quiz question which was something along the lines of "what's the largest number of page faults can a single (valid) instruction cause" and the answer was surprisingly large (in the region of 50+ although I can no longer remember the details.

I would have thought a lot more than that, for string instructions with long operands.

Re the STAR thing, that reminds me of a bug I encountered a decade or so ago on a high end MIPS architecture processor whose manufacturer shall remain nameless.  It would prefetch instructions, issuing memory reads to fill the cache if necessary.  So far so good.  But if you hit a backward branch and then a prefetch for an address past that branch completed, the CPU would consider that access wasted and throw away the data.  It wouldn't put it in the cache -- so the next time through the loop you'd get that memory reference again, and again, every iteration.

This actually broke things in a cache flush operation because that required the execution of some intensely hairy code that was required to run without any extra cache misses.  This bug meant that you'd always get a cache miss at the end of the loop.  The fix required some additional very hairy code to hop ahead through address space to get those cache lines actually into the cache...


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