How were 32-bit minis built in the 70s/80?

[allison]

On 05/11/2019 09:30 PM, ben via cctalk wrote:
> On 5/11/2019 6:28 PM, allison via cctalk wrote:
> 
>> Not all were 74181 based, Thats an early 1972 part and but 1975 it was
>> already getting old though useful as it evolved to 74S and 74F series.
>> The 82s100 and 105 series were out there and even by 1980 the AMD 2900C
>> series was getting long in the tooth. Mask programable gate arrays were
>> in the 1000 and up gate level by 1980 and growing by doubles every 6
>> months to a year. Don't got get programmables like PAL/GAL logic.
>> There was a lot of designs and even inside DEC you might see several
>> approaches depending on what machine and the specific date.  For example
>> the 780, 750 and 730 used very different technology.  I will not go into
>> those that also went the ECL {10K, 100K, 1M families] route.
> 
> 74181 is FAST, but I disagree with the way most computer architecture is

TTl in general is slow a ALU based on 181 is hitting the wall at 5mhz
with 12 or 32 but carry lookahead.


> designed. You have a fast micro code cycle, that is out of sync with
> main memory, that tries to emulate a Harvard? Memory model.
> It looks fast only on paper or demo programs sadly.
> The few schematics I have seen (PDP 8/11) have 74H logic hidden
> inside so you can't say they are pure TTL logic.

Yes, they are mostly TTL and the typical 8efm use MSI ttl such as
7481, a bunch of them.

I'm likely one of the few that took a 8E and ran semiconductor ram then
pushed the clock up to the breaking point and you get to about 4x and
you start getting timing errors and critical path delays that mess with
the logic.  However at 4X you doing a lot and decently fast but you
needs a faster generation of logic.

> 
>  A cpu instruction has 4 parts in general
>  a) getting the instruction and literal data from memory
>  b) calculating the the effective address
>  c) fetching the data from memory  c) ouputing data
>  d) using the data d) saving to memory.
> 
Many of those things can be done in parallel.

Whoever RMW cycles on memory even with very fast memory will slow the
system as you have cycles that cannot be interrupted mostly in the
slow memory.

> It is very hard to speed up this cycle because this has
> sync to extenal memory. Memory is the bottleneck
> is the true speed limit in any sytem. Add in virtual
> memory and in multitasking and graphics
> no wonder the PDP 8 at with TTL gives better response
> time.

Memory is often the bottleneck then IO especially block IO.

The response time of PDP8 was mostly due to a simple OS and nothing to
get in the way.

The name for that is system overhead and PDP-8 had little and what it
did have was written in assembler for speed and compact code as it was
also space constrained.

Allison, have the shirt.

> Ben.
> PS: this message was delayed for about a minute as
> background program froze the sytem.
>