OT? Upper limits of FSB

[alan at alanlee.org]

I'll assume you've read:

https://en.wikipedia.org/wiki/Front-side_bus

Even though synchronization base clocks have remained low, parallel 
buses can run up in the low GHz range (sub 4) in terms of data line 
transitions per second with as many as 128 parallel wires in sync.  It's 
not just FSBs, memory is the same way.  While parasitic effects do 
affect the limit.  Routing 192, 288, etc wires in parallel with matched 
trace length on a PCB to get arrival times in-phase has been a large 
problem as well.  So the trend is rather than running more and more 
wires in parallel with synchronized transfers across the entire span, 
span are being broken up into smaller and smaller units that run either 
unsynchronized or with their own timing delays.  Even with memory - 
starting with DDR3 - each byte group is 'trained' separately by the 
controller and can run at different phase offsets to match the trace 
group routing.  And parallel FSBs have been replaced with <n> number of 
differential pairs running independently as the data is queued and 
reassembled on the receiving end (QPI & HyperTransport).

Same trend in I/O buses starting with PCIe.  Instead of 64 wires @ 66 
MHz in PCI-X, a dual lane PCIe gen 1.0 link can handle a similar load 
with just 6 wires.

-Alan


On 2019-01-05 02:02, Jeffrey S. Worley via cctalk wrote:
> Apropos of nothing, I've been confuse for some time regarding maximum
> clock rates for local bus.
> 
> My admittedly old information, which comes from the 3rd ed. of "High
> Performance Computer Architecture", a course I audited, indicates a
> maximum speed on the order of 1ghz for very very short trace lengths.
> 
> Late model computers boast multi-hundred to multi gigahertz fsb's.  Am
> I wrong in thinking this is an aggregate of several serial lines
> running at 1 to 200mhz?  No straight answer has presented on searches
> online.
> 
> So here's the question.  Is maximum fsb on standard, non-optical bus
> still limited to a maximum of a couple of hundred megahertz, or did
> something happen in the last decade or two that changed things
> dramatically?  I understand, at least think I do, that these
> ridiculously high frequency claims would not survive capacitance issues
> and RFI issues. When my brother claimed a 3.2ghz bus speed for his
> machine I just told him that was wrong, impossible for practical
> purposes, that it had to be an aggregate figure, a 'Pentium rating'
> sort of number rather than the actual clock speed.  I envision
> switching bus tech akin to present networking, paralleled to sidestep
> the limit while keeping pin and trace counts low.....?  Something like
> the PCIe 'lane' scheme in present use?  This is surmise based on my own
> experience.
> 
> When I was current, the way out of this limitation was fiber-optics for
> the bus.  This was used in supercomputing and allowed interconnects of
> longer length at ridiculous speeds.
> 
> Thanks for allowing me to entertain this question.  Though it is not
> specifically a classic computer question, it does relate to development
> and history.
> 
> 
> 
> Best,
> 
> Technoid Mutant (Jeff Worley)