OT? Upper limits of FSB

[Eric Smith]

On Sat, Jan 5, 2019, 00:02 Jeffrey S. Worley via cctalk <
cctalk at classiccmp.org> wrote:

> Apropos of nothing, I've been confuse for some time regarding maximum
> clock rates for local bus.
>
> My admittedly old information, which comes from the 3rd ed. of "High
> Performance Computer Architecture", a course I audited, indicates a
> maximum speed on the order of 1ghz for very very short trace lengths.
>
> Late model computers boast multi-hundred to multi gigahertz fsb's.  Am
> I wrong in thinking this is an aggregate of several serial lines
> running at 1 to 200mhz?  No straight answer has presented on searches
> online.
>

Each individual lane of PCIe gen 3 has one each transmit and receive
differential pair which operate at a serial rate of 8 Gbps each. Gen 4 will
be 16 Gbps. About 1.5% of that gets taken up by the 128b/130b line code
overhead. There is additional overhead consumed by transaction framing,
which means that long burst transfers will get much higher performance than
individual 64-bit or smaller reads and writes.

Doing those data rates with a multi-drop bus like legacy ISA or PCI would
be almost impossible. Parallel multi-drop busses maxed out below 200 MHz.
There are two tricks that make PCIe work:

1) PCIe is not a bus. It consists of strictly point-to-point links, with
tightly controlled impedance.

2) PCIe multi-lane logical links don't assume any phase relationships
between the lanes as a parallel bus would, so there is little or no problem
with timing skew between lanes. The lanes are serialized and deserialized
separately at the endpoints, and higher-level logic in the endpoints is
responsible for distributing the data across the lanes of multi-lane links.

If you have a motherboard with a 16 lane PCIe slot, two 4 lane slots, and
two 1 lane slots, every one of the 26 lanes is an electrically separate set
of point-to-point receive and transmit differential pairs.

The way the chipset is wired makes all of these electrically independent
PCIe lanes collectively act like a "bus" as viewed by the processor (or
north bridge) and PCIe devices.