PDP-11/45 RSTS/E boot problem

Fritz Mueller fritzm at fritzm.org
Wed Feb 6 19:11:05 CST 2019

>> On Feb 6, 2019, at 2:24 PM, Brent Hilpert via cctalk <cctalk at classiccmp.org> wrote:
>> Is the schematic available for the memory board at-issue?
>> Curious myself to see what approach for refresh DEC used.
> Yes, here: http://bitsavers.trailing-edge.com/pdf/dec/pdp11/memory/MP00672_MS11L_engDrw.pdf

For completeness, from the technical manual:

"The refresh logic, shown in sheet 6 of the print set, generates REF CLK H and the refresh address. Sig- nal REF CLK H is derived from a 555 timer (E5) which is set up as a free running oscillator, powered by the + IS V / + 12 V module input (V-555). The REF CLK H signal oscillates with a period of 14.5us and has a positive pulse width of 6us during each period."

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