How do they make Verilog code for unknown ICs?

[Peter Corlett]

On Mon, Jun 20, 2016 at 01:35:46PM -0600, Swift Griggs wrote:
[...]
> Why are folks referring to "Verilogging" and "doing a verilog" on older
> chips. Is there some way you can stuff an IC into a socket or alligator clip
> a bunch of tiny leads onto it and then "map" it somehow into Verilog?

Only for trivial chips that do not maintain (much) state, such as ROMs and 74xx
chips which (almost) always generate the same output for a given set of inputs,
so it is possible to exhaustively search all of the possible states.

Useful chips use RTL[0] designs which contain registers (aka latches,
flip-flops, etc) that hold internal state. The outputs now vary not only on the
inputs but also on the registers, and there are far to many states to be able
to search them all. An example of a chip that makes heavy use of registers is a
CPU itself, and it is not plausible to try and automatically figure out the
instruction set of a novel CPU based just on its bus interface.

In practice, one would hoover up as much documentation as possible and come up
with a prototype in HDL that implements the inferred spec, then compare it
against how the real chip works. This will almost certainly not work first
time, so one then gets to fix the bugs and iterate until the copy is good
enough for the given application. This is the sort of thing that effortlessly
soaks up man-years of effort.


[0] https://en.wikipedia.org/wiki/Register-transfer_level