FPGA I/O and external memory (was Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?)

[Eric Smith]

On Mon, Jun 20, 2016 at 10:07 PM, ben <bfranchuk at jetnet.ab.ca> wrote:
> Do you use Static or Dynamic ram with the FPGA's?

I've done both.

You indicated that you wanted 5V I/O. AFAIK, there haven't been any
new FPGAs made in many years that have even 5V-tolerant I/O, let alone
actual 5V I/O.  Some really old FPGAs may still be in production, but
are not very cost-effective. The latest midrange to high-end FPGAs
aren't even 3.3V-tolerant. However, the economy FPGAs such as Spartan
6 and Artix 7 still support 3.3V I/O, and are quite inexpensive for
the amount of resources provided.

For 5V-tolerance, it is usually adequate to use 3.3V I/O with series
resistors to limit the current. Xilinx specifies a maximum rated
current for the clamp diodes.  This works fine when interfacing actual
TTL (or TTL-compatible MOS) parts. It is NOT adequate for driving 5V
CMOS, such as CD4000 series, because the FPGA won't drive above 3.3V,
and the 5V CMOS inputs typically are specified for Vih min of 90% of
Vdd, which is 4.5V.

The series resistor does slow down the signal, which usually isn't a
problem with TTL since TTL is quite slow by FPGA standards. Where it
is a problem, an nFET voltage clamp can be used instead.