Qbus split I&D?

Noel Chiappa jnc at mercury.lcs.mit.edu
Wed Mar 18 10:16:02 CDT 2015

    > From: Paul Koning

    > if the CPU generates an address in the range 17000000 to 17577777, it
    > lands on the Unibus and is then mapped by the Unibus map.

Umm, I think you meant "to 17 757 777", no? (Too many 7's - I find it helpful
to break them up into groups of 3, the way DEC does, to prevent that kind of

    > More precisely, it works that way for 11/44 and 11/70 - but not for the
    > J-11. That's a difference not documented in the PDP-11 Architecture
    > handbook model differences table

But, but, but... the J-11 doesn't _have_ a UNIBUS map! Well, the 11/84 and
11/94 do, but not other J-11 machines. (And the Architecture Handbook table
does not have separate columns for the 11/73, 11/84, etc.) So an 11/73 can't
have a reference in the range 17 000 000 to 17 757 777 go out the UNIBUS -
there isn't one! :-)

So what happens if one does a reference to something in the range 17 000 000
to 17 757 777 on the 11/84? The 11/84 _does_ support having memory on the
UNIBUS (up to 248KB), _but_ how it appears depends on how much there is. (See
section 3.13.2, EK-1184-TM-PR2.) There's a special register to configure it
(the 'KTJ11-B Memory Configuration Register', KMCR), which includes _how
much_ UNIBUS memory there is.

If there is _no_ UNIBUS memory, then PMI memory appears (to the CPU) at 0 up,
and the UNIBUS Map is enabled. References to 17 000 000 to 17 757 777 go to
PMI memory ("PMI memory, as seen by the CPU, resides in contiguous locations
from 0 up to as high as 17 757 777"), and presumably if there is no PMI
memory there, they fail, they don't even go out the UNIBUS to see if anyone's

If there is _no_ PMI memory, then _UNIBUS_ memory appears (to the CPU) at 0
up, and the UNIBUS Map is _disabled_. (And I assume references to the range
01 000 000 to 17 757 777 just immediately fail.)

If, on the other hand, there is a _mix_ of PMI and UNIBUS memory, things get
really wierd. UNIBUS memory does not appear at 0, _or_ at 17 000 000 up to 17
577 777; instead, that memory appears to the CPU (depending on how much there
is) from 17 757 777 _downwards_ to (17 600 000-UNIBUS_memory_size); UNIBUS
memory apparently has to be assigned UNIBUS addresses from 757 777 _down_
("[UNIBUS] DMA Address XXX XXX accesses the same UNIBUS Memory location
accessed by CPU addresses 17 XXX XXX").

(Which is slightly odd because in the case where there is no PMI memory, the
UNIBUS memory needs to be assigned UNIBUS addresses from 0 up, which is quite
different from how to assign UNIBUS addresses to that memory in the 'mixed'
case. But never mind... :-)

The UNIBUS map will not respond to UNIBUS cycles in the address range
assigned to the UNIBUS memory.

And, to look at the original point, I would _guess_ that references to
locations in the range 17 000 000 to 17 757 777, but below the configured
UNIBUS memory, again don't go out the UNIBUS, but try and perform a PMI
cycle, which may or may not fail.

Basically, it seems like DEC was determined not to waste any address space on
the J-11/UNIBUS machines. Either it's configured as UNIBUS memory, or it's

The KTJ11-B can also be configured to operate in 18-bit mode, with a mix of
PMI and UNIBUS memory, but I will leave the ugly details unless someone is
particularly interested in them! :-)


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