Qbus split I&D?

[Eric Smith]

Noel Chiappa wrote:
> I have this dream of one day having an 11/45, with the Enable and the optional
> cache.Now that would be a sweeet machine: most of the capability of an 11/70,
> but a lot less power draw.

The power draw of the 11/45 and 11/70 is almost the same, with the
exception of the separate memory box(es), MJ11 core or MK11 MOS, for
the 11/70. I'd *much* rather have an 11/70 with third-party memory
than an 11/45 with any amount of third-party enhancements. The PEP70
was a single-board memory that you could plug into an otherwise unused
slot in the 11/70 CPU backplane, with a few extra wire-wrapped jumpers
on the backplane, and plug in the four ribbon cables from the 11/70
cache modules. The same vendor also offered an HC70 "HyperCache"
option, which when used in conjunction with the PEP70, made all memory
operate at cache speed.

It would probably be difficult or impossible to obtain a PEP70 (with
or without HC70) at this late date. The 11/70 memory bus (between the
CPU and memory box) is quite simple, so it should be very easy for
someone with reasonable hardware expertise to design and build a
modern memory board for it, comparable to the PEP70.