9 Jul
2023
9 Jul
'23
3:38 p.m.
Hello,
I have a non-functioning VT100. I think I may have isolated the problem to
an Intel 8228 chip (or 88228, the schematic says 8228, the part is marked
88228C). Certainly, the part gets a bit hot and it doesn't seem to be
outputting anything on the I/O W pin (pin 27) despite activity on STSTB (pin
1), DBIN (pin 4) and WR (Pin 3). There is no activity on the HLDA input
though, but I am not sure if that is required because I think the firmware
is just trying to send its status to the keyboard LEDs.
I can find a brief datasheet for the 8228 but it doesn't tell me the logic
for producing the I/O W signal, so I am not sure if it is behaving as it
should. Does anyone have more comprehensive information on how the 8228 is
supposed to work?
I have dumped the ROMs and been able to capture the ROM reads and they match
the disassembled code, so I think the 8080 CPU itself is working.
Thanks
Rob
9 Jul
9 Jul
4:12 p.m.
Actually I have just found a more detailed description in the Intel 8080
Microcomputer Systems Users Manual 1975, but it still doesn't tell me
exactly how it works. It isn't completely clear to me if it needs HLDA to be
asserted for I/O W to be asserted.
-----Original Message-----
From: Rob Jarratt via cctalk <cctalk(a)classiccmp.org>
Sent: Sunday, July 9, 2023 4:39 PM
To: General Discussion: On-Topic and Off-Topic Posts
<cctalk(a)classiccmp.org>
Cc: Rob Jarratt <robert.jarratt(a)ntlworld.com>
Subject: [cctalk] VT100: Datasheet for Intel 8228
Hello,
I have a non-functioning VT100. I think I may have isolated the problem to
an
Intel 8228 chip (or 88228, the schematic says 8228,
the part is marked
88228C). Certainly, the part gets a bit hot and it doesn't seem to be
outputting anything on the I/O W pin (pin 27) despite activity on STSTB
(pin
1), DBIN (pin 4) and WR (Pin 3). There is no activity
on the HLDA input
though, but I am not sure if that is required because I think the firmware
is
just trying to send its status to the keyboard LEDs.
I can find a brief datasheet for the 8228 but it doesn't tell me the logic
for
producing the I/O W signal, so I am not sure if it is
behaving as it
should.
Does anyone have more comprehensive information on how
the 8228 is
supposed to work?
I have dumped the ROMs and been able to capture the ROM reads and they
match the disassembled code, so I think the 8080 CPU itself is working.
Thanks
Rob
4:18 p.m.
HLDA should be deasserted, that puts the processor in a DMA mode where it releases all the
control signals.
I/O W is asserted low when OUT is high and the low WR pulse comes along. It's both
status and timing, coming out of the 8228.
You would probably do well seeing if MEMR and MEMW are asserting. If the program is
running off due to e.g. bad RAM, ROM bitrot, etc. you may never see the I/O lines assert.
Thanks,
Jonathan
------- Original Message -------
On Sunday, July 9th, 2023 at 12:12, Rob Jarratt via cctalk <cctalk(a)classiccmp.org>
wrote:
Actually I have just found a more detailed description in the Intel 8080
Microcomputer Systems Users Manual 1975, but it still doesn't tell me
exactly how it works. It isn't completely clear to me if it needs HLDA to be
asserted for I/O W to be asserted.
-----Original Message-----
From: Rob Jarratt via cctalk cctalk(a)classiccmp.org
Sent: Sunday, July 9, 2023 4:39 PM
To: General Discussion: On-Topic and Off-Topic Posts
cctalk(a)classiccmp.org
Cc: Rob Jarratt robert.jarratt(a)ntlworld.com
Subject: [cctalk] VT100: Datasheet for Intel 8228
Hello,
I have a non-functioning VT100. I think I may have isolated the problem to
an
Intel 8228 chip (or 88228, the schematic says
8228, the part is marked
88228C). Certainly, the part gets a bit hot and it doesn't seem to be
outputting anything on the I/O W pin (pin 27) despite activity on STSTB
(pin
1), DBIN (pin 4) and WR (Pin 3). There is no
activity on the HLDA input
though, but I am not sure if that is required because I think the firmware
is
just trying to send its status to the keyboard
LEDs.
I can find a brief datasheet for the 8228 but it doesn't tell me the logic
for
producing the I/O W signal, so I am not sure if
it is behaving as it
should.
> Does anyone have more comprehensive information on how the 8228 is
> supposed to work?
>
> I have dumped the ROMs and been able to capture the ROM reads and they
> match the disassembled code, so I think the 8080 CPU itself is working.
>
> Thanks
>
> Rob
7:51 p.m.
Thanks for confirming that HLDA doesn't need to be asserted at this stage.
I looked at the address trace and matched it to the disassembled ROM. My ROM image
compares to another ROM image that has been posted online at 9track.net, so I am fairly
confident that the CPU and ROM are OK.
I don't think that the RAM test is passing though, it might not even be able to start
it, I have not traced this sufficiently to be sure, but it is in a loop at one point, but
not before sending data to the keyboard UART. That is what made me look at the 8228
because I traced back that far to where something did not seem be happening correctly.
In fact, I now realise that I should have checked MEM WR and MEM RD. I can see that MEM WR
is never asserted, but MEM RD is asserted. I do see WR being asserted on the input side
immediately after startup, but then it isn't asserted again.
It is possible that the firmware is in a loop before it gets to the RAM test, possibly
because the 8228 driver is not working.
Regards
Rob
-----Original Message-----
From: Jonathan Chapman <lists(a)glitchwrks.com>
Sent: Sunday, July 9, 2023 5:18 PM
To: rob(a)jarratt.me.uk; General Discussion: On-Topic and Off-Topic Posts
<cctalk(a)classiccmp.org>
Subject: Re: [cctalk] Re: VT100: Datasheet for Intel 8228
HLDA should be deasserted, that puts the processor in a DMA mode where it
releases all the control signals.
I/O W is asserted low when OUT is high and the low WR pulse comes along.
It's both status and timing, coming out of the 8228.
You would probably do well seeing if MEMR and MEMW are asserting. If the
program is running off due to e.g. bad RAM, ROM bitrot, etc. you may never
see the I/O lines assert.
Thanks,
Jonathan
------- Original Message -------
On Sunday, July 9th, 2023 at 12:12, Rob Jarratt via cctalk
<cctalk(a)classiccmp.org> wrote:
Actually I have just found a more detailed description in the Intel
8080 Microcomputer Systems Users Manual 1975, but it still doesn't
tell me exactly how it works. It isn't completely clear to me if it
needs HLDA to be asserted for I/O W to be asserted.
working.
> >
> > Thanks
> >
> > Rob -----Original Message-----
From: Rob Jarratt via cctalk cctalk(a)classiccmp.org
Sent: Sunday, July 9, 2023 4:39 PM
To: General Discussion: On-Topic and Off-Topic Posts
cctalk(a)classiccmp.org
Cc: Rob Jarratt robert.jarratt(a)ntlworld.com
Subject: [cctalk] VT100: Datasheet for Intel 8228
Hello,
I have a non-functioning VT100. I think I may have isolated the
problem to
an
Intel 8228 chip (or 88228, the schematic says
8228, the part is
marked 88228C). Certainly, the part gets a bit hot and it doesn't
seem to be outputting anything on the I/O W pin (pin 27) despite
activity on STSTB
(pin
1), DBIN (pin 4) and WR (Pin 3). There is no
activity on the HLDA
input though, but I am not sure if that is required because I think
the firmware
is
just trying to send its status to the keyboard
LEDs.
I can find a brief datasheet for the 8228 but it doesn't tell me the
logic
for
producing the I/O W signal, so I am not sure if
it is behaving as it
should.
> Does anyone have more comprehensive information on how the 8228 is
> supposed to work?
>
> I have dumped the ROMs and been able to capture the ROM reads and
> they match the disassembled code, so I think the 8080 CPU itself is
16 Jul
16 Jul
5:13 p.m.
I used a logic analyser to check the 8228 and it does appear to be working as expected as
can be seen here https://rjarratt.files.wordpress.com/2023/07/8228-operation.jpg. The
labels are not very clear, but the 3rd from top is the WR input and the 4th from top is
the I/O W output. So it does look like it is working.
The odd thing is that I can't pick this up with my DSO. I have tried messing with the
trigger, but I just can't pick up anything that shows I/O W going low. I am using -ve
edge triggers. I have tried a pulse trigger with a width >20ns and I have tried nth
edge trigger, neither of the latter two ever trigger. Obviously it is my method that is
wrong, but I really don't know what it is about my method that is wrong. Are there any
common mistakes that novices make?
Thanks
-----Original Message-----
From: Rob Jarratt <robert.jarratt(a)ntlworld.com>
Sent: 09 July 2023 20:51
To: 'Jonathan Chapman' <lists(a)glitchwrks.com>om>; rob(a)jarratt.me.uk;
'General Discussion: On-Topic and Off-Topic Posts' <cctalk(a)classiccmp.org>
Subject: RE: [cctalk] Re: VT100: Datasheet for Intel 8228
Thanks for confirming that HLDA doesn't need to be asserted at this stage.
I looked at the address trace and matched it to the disassembled ROM. My
ROM image compares to another ROM image that has been posted online at
9track.net, so I am fairly confident that the CPU and ROM are OK.
I don't think that the RAM test is passing though, it might not even be able to
start it, I have not traced this sufficiently to be sure, but it is in a loop at one
point, but not before sending data to the keyboard UART. That is what made
me look at the 8228 because I traced back that far to where something did
not seem be happening correctly.
In fact, I now realise that I should have checked MEM WR and MEM RD. I can
see that MEM WR is never asserted, but MEM RD is asserted. I do see WR
being asserted on the input side immediately after startup, but then it isn't
asserted again.
It is possible that the firmware is in a loop before it gets to the RAM test,
possibly because the 8228 driver is not working.
Regards
Rob
-----Original Message-----
From: Jonathan Chapman <lists(a)glitchwrks.com>
Sent: Sunday, July 9, 2023 5:18 PM
To: rob(a)jarratt.me.uk; General Discussion: On-Topic and Off-Topic
Posts <cctalk(a)classiccmp.org>
Subject: Re: [cctalk] Re: VT100: Datasheet for Intel 8228
HLDA should be deasserted, that puts the processor in a DMA mode where
it releases all the control signals.
I/O W is asserted low when OUT is high and the low WR pulse comes
along.
> It's both status and timing, coming out of the 8228.
>
> You would probably do well seeing if MEMR and MEMW are asserting. If
> the program is running off due to e.g. bad RAM, ROM bitrot, etc. you
> may never see the I/O lines assert.
>
> Thanks,
> Jonathan
>
> ------- Original Message -------
> On Sunday, July 9th, 2023 at 12:12, Rob Jarratt via cctalk
> <cctalk(a)classiccmp.org> wrote:
>
>
> >
> >
> > Actually I have just found a more detailed description in the Intel
> > 8080 Microcomputer Systems Users Manual 1975, but it still doesn't
> > tell me exactly how it works. It isn't completely clear to me if it
> > needs HLDA to be asserted for I/O W to be asserted.
> >
> > > -----Original Message-----
> > > From: Rob Jarratt via cctalk cctalk(a)classiccmp.org
> > > Sent: Sunday, July 9, 2023 4:39 PM
> > > To: General Discussion: On-Topic and Off-Topic Posts
> > > cctalk(a)classiccmp.org
> > > Cc: Rob Jarratt robert.jarratt(a)ntlworld.com
> > > Subject: [cctalk] VT100: Datasheet for Intel 8228
> > >
> > > Hello,
> > >
> > > I have a non-functioning VT100. I think I may have isolated the
> > > problem to
> >
> > an
> >
> > > Intel 8228 chip (or 88228, the schematic says 8228, the part is
> > > marked 88228C). Certainly, the part gets a bit hot and it doesn't
> > > seem to be outputting anything on the I/O W pin (pin 27) despite
> > > activity on STSTB
> >
> > (pin
> >
> > > 1), DBIN (pin 4) and WR (Pin 3). There is no activity on the HLDA
> > > input though, but I am not sure if that is required because I
> > > think the firmware
> >
> > is
> >
> > > just trying to send its status to the keyboard LEDs.
> > >
> > > I can find a brief datasheet for the 8228 but it doesn't tell me
> > > the logic
> >
> > for
> >
> > > producing the I/O W signal, so I am not sure if it is behaving as
> > > it
> >
> > should.
> >
> > > Does anyone have more comprehensive information on how the 8228 is
> > > supposed to work?
> > >
> > > I have dumped the ROMs and been able to capture the ROM reads and
> > > they match the disassembled code, so I think the 8080 CPU itself
> > > is
> working.
> > >
> > > Thanks
> > >
> > > Rob 
17 Jul
17 Jul
5:24 a.m.
Common DSO trigger problems experienced by a novice are:
1) Trigger position is off the screen. The trigger position relative to the
current visible capture is typically shown somewhere on the screen - often
at the top of the screen. Reduce the horizontal resolution to something
like 10 ms/division and then scroll the trigger position to be in the exact
centre of the screen and then increase the horizontal resolution to
something suitable e.g 500 ns/division. Typically the DSO will keep the
trigger position centred if you had it close enough to the centre position
before increasing the horizontal resolution.
2) The horizontal resolution is set so that the pulse is invisible. For
example 1 ms/division for a 10 ns pulse.
3) Triggering on the wrong channel.
4) Trigger level above or below the signal.
5) Trigger mode set to "Auto" as opposed to "Normal" or
"Single" causing a
momentary display of the triggered signal which is immediately overwritten
by the current signal.
Tom Hunter
On Mon, Jul 17, 2023 at 1:14 AM Rob Jarratt via cctalk <
cctalk(a)classiccmp.org> wrote:
I used a logic analyser to check the 8228 and it does
appear to be working
as expected as can be seen here
https://rjarratt.files.wordpress.com/2023/07/8228-operation.jpg. The
labels are not very clear, but the 3rd from top is the WR input and the 4th
from top is the I/O W output. So it does look like it is working.
The odd thing is that I can't pick this up with my DSO. I have tried
messing with the trigger, but I just can't pick up anything that shows I/O
W going low. I am using -ve edge triggers. I have tried a pulse trigger
with a width >20ns and I have tried nth edge trigger, neither of the latter
two ever trigger. Obviously it is my method that is wrong, but I really
don't know what it is about my method that is wrong. Are there any common
mistakes that novices make?
Thanks
20 Jul
20 Jul
8:08 p.m.
Thanks for the suggestions but I think I was already aware of all of those. I have double
checked against your list and still don’t see the pulses with the DSO. There has to be
something else I am doing wrong ☹
From: Tom Hunter <ccth6600(a)gmail.com>
Sent: 17 July 2023 06:24
To: rob(a)jarratt.me.uk; General Discussion: On-Topic and Off-Topic Posts
<cctalk(a)classiccmp.org>
Subject: Re: [cctalk] Re: VT100: Datasheet for Intel 8228
Common DSO trigger problems experienced by a novice are:
1) Trigger position is off the screen. The trigger position relative to the current
visible capture is typically shown somewhere on the screen - often at the top of the
screen. Reduce the horizontal resolution to something like 10 ms/division and then scroll
the trigger position to be in the exact centre of the screen and then increase the
horizontal resolution to something suitable e.g 500 ns/division. Typically the DSO will
keep the trigger position centred if you had it close enough to the centre position before
increasing the horizontal resolution.
2) The horizontal resolution is set so that the pulse is invisible. For example 1
ms/division for a 10 ns pulse.
3) Triggering on the wrong channel.
4) Trigger level above or below the signal.
5) Trigger mode set to "Auto" as opposed to "Normal" or
"Single" causing a momentary display of the triggered signal which is
immediately overwritten by the current signal.
Tom Hunter
On Mon, Jul 17, 2023 at 1:14 AM Rob Jarratt via cctalk <cctalk(a)classiccmp.org
<mailto:cctalk@classiccmp.org> > wrote:
I used a logic analyser to check the 8228 and it does appear to be working as expected as
can be seen here https://rjarratt.files.wordpress.com/2023/07/8228-operation.jpg. The
labels are not very clear, but the 3rd from top is the WR input and the 4th from top is
the I/O W output. So it does look like it is working.
The odd thing is that I can't pick this up with my DSO. I have tried messing with the
trigger, but I just can't pick up anything that shows I/O W going low. I am using -ve
edge triggers. I have tried a pulse trigger with a width >20ns and I have tried nth
edge trigger, neither of the latter two ever trigger. Obviously it is my method that is
wrong, but I really don't know what it is about my method that is wrong. Are there any
common mistakes that novices make?
Thanks
490
days inactive
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6 comments
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Tom Hunter