On Thu, Mar 9, 2023 at 5:05 PM Cameron Kaiser via cctalk <cctalk(a)classiccmp.org> wrote: We had an Amdahl in the middle of a multi-thousand-square-foot computer room (one of several) at work 25 years ago. I do not know/remember the model number but it was made of up several cabinets not in a line. It had such a convoluted layout that you could literally stand in the "middle" of it and not see outside. If you stood in exactly the right spot, the blank panels lined up and made the visual appearance of a box with no exits. You _could_ get lost in that one, as long as you didn't take half a step away. -ethan

On Thu, Mar 16, 2023 at 9:38 PM Ethan Dicks via cctalk <cctalk(a)classiccmp.org> wrote: Heh, of the limited number of big Mainframe data centers I got to visit, every one had one big red Amdahl box among a vast field of IBM hardware. Once you had enough IBM systems IBM just assumed you were their bitch now and would pay whatever they asked for further systems. The solution was to buy a single Amdahl system thus getting your IBM sales rep summerily replaced with a much humbler one. G.

On Thu, 9 Mar 2023, Steve Lewis via cctalk wrote: What is the ORIGIN of the term "mainframe"? Keep in mind that the term "Mini Computer" was invented by marketing people to be able to sell/rent computers to small businesses whose needs were small. LATER, it became obvious that many small businesses that succombed to the sales pitches for minicomputers were even better served by microcomputers, particularly several dedicated ones. Accounting needed a computer, but not much of one; payroll of even a few employees ends up requiring an accountant. And, inventory could use a computer, etc. If there is a graphic arts department, they could use a computer, but with seriously different characteristics. There was s'posedly some internal political issues at IBM about whether the Entry Systems Division (5150, etc.) would cut into the other depaartments.

Steve Lewis wrote: You may find people will disagree with that. I'm not sure what mainframe means either, but I'm asking around. Pysical size, I/O capacity, CPU offload to front ends, and users served seem to factor into it. I believe the term minicomputer was first applied to the PDP-8. It was kind of retroactively applied going back to the PDP-1. Whether the PDP-10 is a mini is sometimes hotly debated. IBM people say no, DEC peole say yes. Kind of yes, but recally early computers were often operated in batch mode. Minis would typically do one task, or handle a few users. Consider that a minicomputer is larger than microcomputer. I don't think that does a service to anyone.

On 3/10/2023 1:39 AM, Lars Brinkhoff via cctalk wrote: The first mainframe I worked on was single user, single tasking and all jobs were submitted as "batch" as in a batch of cards.  :-) Second Mainframe I worked on supported lots of users but to the user it was still small amount of interactive and the rest batch.  multi-user was done thru VM370 which made it look like we all were the only users on out machine. Third Mainframe I worked on  was primarily interactive with many user during the day and then ran lots of batch jobs at night. The first minis I worked on all supported lots of users and many simultaneous tasks.  Except the VAX when someone decided to run the Ada compiler and the machine ground to a halt so we all logged off and found something else to do. :-) Is is?  I have had PC's that were larger than some of the Minis I worked on. This whole mess is to complicated to ever sort out and loaded with more opinion than fact.  Probably because in reality all three terms are marketing speak and don't have real, verifiable definitions. bill

You mean DOS/360 as opposed to OS/360? I don't know that one. But OS/360 came in three flavors: PCP, MFS, and MVS. PCP was strictly single user with unit record I/O direct from/to the devices (no spooling). If you had enough memory you could run the multi-tasking OS variants, MFS or MVS. On the 360 model 44 we used in college we didn't have enough memory so we were stuck with PCP. It was interesting to realize IBM stuck people with the rough analog of RT-11 on a 128 kB machine -- twice the memory size that on a PDP-11 would support a 16 user timesharing system. Apart from the lack of concurrency and no spooling, PCP also didn't have timers. We ran a lot of WATFIV (successor of WATFOR, a fast Fortran compiler for educational use), but that would run a whole stack of programs as a single OS job, using the timer to limit individual program. PCP wouldn't support that so a stuck student program would force the canceling of the whole job, then finding where in the stack of cards to resume and reload. Ugh. I figured out how to hook to the interrupt vector of the "interrupt" button on the operator console panel (using a simple security defect in ECXP appendages), then tied that to the timer expiration in WATFIV. With that, the operator could kill a stuck student program with a single button push and WATFIV would go on to the next. paul

On 3/10/23 13:00, Paul Koning via cctalk wrote: MFT was Multiprogramming with a Fixed number of Tasks, MVT was Multiprogramming with a Variable number of Tasks.  MFT had "fixed" partitions, although the operator could "drain" partitions and then rearrange them manually.  MVT automatically rearranged partitions by looking at the memory requirements of the next-up programs in the queue.  Well, that all sounds great, except that allowing the user to ask for completely random partition sizes ended up filling memory with little chunks of odd-size partitions that left memory fragmented.  So, the fix was to only allow partition sizes in some standard quanta like 50 K.  If you asked for 37 K you would run in a 50K partition and be charged for it. MVS was a 370 OS. Jon

On 3/10/23 20:13, Gavin Scott via cctalk wrote: The 1620's I resurrected at USL in Lafayette, La. were card in and out.  There was also a printer.  It had an assembler deck and a Fortran compiler. I suspect that the 360 would have slipped in there except for the fun getting arithmetic to match on the machines. Had 2 cpus,  one card reader / punch and a printer for the 1620. thanks Jim

Speaking of 1620 peripherals, I know there were paper tape reader/punch options for it. Has anyone ever encountered those in the wild? paul

Dijkstra said as much when he evaluated the 1620 for possible use by the TU Eindhoven -- a big problem is that it was unable to handle arbitrary 8-bit data. paul

On 3/11/23 14:34, Chuck Guzis via cctalk wrote: Perhaps I need to elaborate on my earlier response for those not familiar with the 1620. First of all, the 1620 is a decimal machine, digit addressable with bits CF8421. C is the parity bit and only shows up on the console display--it's not something that a program sees. Second of all, the 1620 has no user-addressable registers--it's all memory-to-memory. Instructions are all 12 digits. Opcode 2 digits, P and Q fields 5 digits each. *Variable word length*, with words being addressed by the low-order digit and with the high-order digit flagged with the F bit. Negative numbers have the F bit set in the lowest order digit. Words may be grouped up into records, addressed by the lowest address of the record and terminated with the record mark (x8x2x). Addition, subtraction and multiplication on the CADET (model 1 1620) is done through tables in low memory, which must be loaded after boot time to get any useful work done. There are two modes for typewriter/printer/card/tape I/O--numeric (each digit represents a character) and alpha (pairs of digits represent characters). There are a a couple of special non-numeric bit combinations--the record mark (x8x2x bits), the numeric blank (x84xx) and the group mark (used for disk I/O) (x842x); any may carry a flag bit. As mentioned, the group mark is used for disk I/O when the contents of a group may contain records. On other I/O devices, the record mark determines the end of a record. There are rules about what can be on odd- or even-address boundaries. for example, an instruction must start on an even address boundary. The numeric blank prints as a space when doing numeric I/O. Otherwise, it cannot be used in math operations, nor can it be generated using them--you read it from an I/O device and move it around. There is no stack,but there is a single register that holds a single return address when a Branch-and-transmit instruction is executed. There is a single instruction that branches to the location held in that register; the register itself is not addressable. You can see that the limit is one call depth using this register--it's most handy when debugging because it can be display on the console lamps. Serious programs usually use the Branch and Transmit Immediate, where the Immediate (Q) field is deposited just ahead of the branch address. The custom is to use this field as a return address for subroutines. The 1620 comes with 20K digits of storage standard, with optional added memory to 40K or 60K digits. The maximum length of a numeric value is 20K digits. Given the variable-length nature of the machine, clearing memory to any value can be done with a single instruction. Hope this provides some background for what irked Dijkgstra. I should note that what I've described describes the Model 1 1620. The model 2 was considerably improved and even had an option for binary manipulation of values. The IBM 1710 was essentially a 1620 with interrupts, added I/O capabilities and a real-time clock and was used for industrial control. --Chuck

I agree entirely. What Dijkstra was doing was evaluating a number of machines to see if they would serve as the university's primary computer. And given the 1620's limitations he had good reason to conclude that it's not well suited for that job. Suited for more limited jobs? Definitely. paul

On Fri, Mar 10, 2023 at 10:21 AM Bill Gunshannon via cctalk < cctalk(a)classiccmp.org&gt; wrote: I declare you the winner here, Bill. Sellam

Still catching up. Lars, you have that backwards. DEC people *know* that the PDP-10 et seq. were mainframes (with the single exception of the DECSYSTEM-2020 office computer), while IBMers don't think anything not built by the Mother Ship is a mainframe (if it was build after the System/360 announcement, which came 3 weeks after the DEC announcement of the PDP-6, also a mainframe). Rich

Apart from spooling, which uncouples slow I/O from execution, there is also "multiprogramming", which means being able to run more than one job concurrently. Timesharing does that, of course, but I think multiprogramming was intended to refer to batch systems that did so. An early example is the famous THE operating system: it spools all I/O and supports three concurrent jobs (two unrestricted and one limited to "small jobs"). It has a number of interesting structural innovations, like a hierarchical design where details are handled in one layer and thereby no longer matter to the layers above. Also semaphores, which it uses throughout, both for internal synchronization and to synchronize with DMA hardware. paul

Where would you put JOSS? (1963) running on Johnniac?

On 3/15/23 17:23, Jon Elson via cctalk wrote: Interrupts with IBM were a "if you need them, we have them". For example, the 1800 (industrial version of the 1130) and the 1710 (industrial version of the 1620) both had realtime clocks and interrupts. I find it interesting, tracing the evolution of Seymour Cray's thinking from the CDC 160A through the Cray 2. One cannot really understand, for example the thinking behind the 7600 without knowing the 6600 and its predecessors. The CDC 1604 (1959 (certainly had interrupts, both internal and external, but I do not believe it had memory protection. It did have a console loudspeaker driven by a 3-bit DAC, however. The CDC 3000 series (1962) had an interrupt capability as well as memory protection and realtime clock. When you get to the CDC 6000 era, the question of interrupts is interesting. Certainly the PPUs didn't have interrupt capability, but the CPU could be exchange-jumped by a PPU (usually PP0) to provide task-switching on demand. In general, however, CPU programs did not implement interrupt-handling as such. It is clear that Seymour initially intended most OS functions to be distributed among the PPs. I do believe that he abandoned that line of thought when it came to the 7600 and beyond. The dominant 7600 OS, SCOPE 2, was an interesting combination of privilege levels and overlapping storage protection. 7600 PPUs could not host an OS because they were confined to fixed buffer addresses in SCM. The 7600 PPs are pretty much confined to I/O. For whatever it's worth, --Chuck

On 3/17/23 06:25, Paul Koning wrote: I assume that you've seen Mark Smotherman's paper on this. UNIVAC seems to hold the distinction. https://people.computing.clemson.edu/~mark/interrupts.html --Chuck

I noticed the section on deferred interrupts, which mentions Cutler and "fork" on RSX. It doesn't mention the similar mechanism, also called fork, in RT-11. I don't know if RT-11 was earlier or concurrent, nor whether the two came up with it independently. paul

The paper mentions it: "fork routines" which I think Linux calls "bottom half". These are functions executed as a consequence of an interrupt, but from a queue and not with interrupts masked off. The idea is that an RTOS doesn't want to block interrupts more than the minimum necessary, so operating systems like RT11 and RSX in their interrupt handler capture the necessary hardware state in memory, then queue a fork routine to do the real work later after interrupts have once again been enabled. This goes by way of what RT11 originally called a "fork queue" but was told to rename to "fork list" :-) Some other operating systems, like RSTS, have some amount of deferred processing but tend to do a lot, often all, the interrupt handling work at interrupt level. That's ok for a timesharing system, but you wouldn't want to run time critical stuff on it. And this is why RSTS does a comparatively poor job of supporting DDCMP over async lines. "Fork" in the Unix sense is something different and unrelated. paul

On interrupt coalescing (mentioned under "performance techniques"), an early -- perhaps first -- implementation is in the Electrologica X8. It uses queues guarded by semaphores to communicate with the I/O coprocessor CHARON, and the interrupts delivered in response are also controlled by a semaphore. The initial count of that semaphore specifies how many I/O operations to complete before an interrupt is done. Its semaphores are constructed around a hardware primitive that adds a register to memory and delivers the result both to that memory location and to the register, interlocked via a read/modify/write core memory cycle. paul

On Wed, Mar 15, 2023 at 4:11 PM Rich Alderson via cctalk < cctalk(a)classiccmp.org&gt; wrote: This, above all other explanations, rings the most true. I remember when the internet and e-mail became all the rage in the late 1990s, everything was eThis and eThat. And when Apple coined the iPhone, everything started to become iThis and iThat. So it makes complete sense that in the era of mini-everything, someone in the computer industry would grab onto the mini-zeitgeist. Thanks for the contributions to the discussion, Rich. Sellam

On Mar 15, 2023, at 3:55 PM, Rich Alderson via cctalk &lt;cctalk(a)classiccmp.org&gt; wrote: The first time I saw a PDP-8 was in the Museum of American History in Washington DC in 1990. Along with a straight-8, they had that marketing photo. Zane

Speaking of pornography, the ad on page 14 of 80 Micro magazine August 1980 was a bit of a shocker. https://archive.org/details/80-microcomputing-magazine-1980-08/page/n13/mod… On Thu, Mar 9, 2023 at 5:40 PM Sellam Abraham via cctalk < cctalk(a)classiccmp.org&gt; wrote:

On 3/9/23 17:33, Jon Elson via cctalk wrote: https://d3i71xaburhd42.cloudfront.net/d7fd7af8c26e659d712bf029d2287c919847e… And that's not counting the stations or SBUs. 1970s. --Chuck

On Thu, 9 Mar 2023, Paul Koning via cctalk wrote: So, what defines a "supercomputer"? Microcomputer Minicomputer mainframe supercomputer "lose a screw" / "lose screwdriver" /"lose scope" / "lose technician" -- Grumpy Ol' Fred cisin(a)xenosoft.com

On 3/9/23 17:56, Paul Koning wrote: The STAR was Jim Thornton's brainchild, so he was quite familiar with the 6000 and 7000 series. I believe that the STAR used 7000 SCM core. Most of the pipeline units were 128 bits wide; caore bus width was 512+SECDED. A fair amount of effort was put into finding something that could feed the "STAR channel" at full bandwidth; hence, the 100K RPM STAR drum and the SCROLL. Neither of which made it out of the lab. It was a system of extremes. Apparently, in the beginning, Fairchild had huge problems producing the chips for the register file (256x64 bits). Neil Lincoln took over the project after Thornton got interested in other things, after the departure of Seymour. I remember seeing an excavator digging a trench around the employee parking lot at ARHOPS for some high-speed network experiments of T's. Not that Neil was a slouch in that department. Witness the liquid nitrogen-cooled ETA-10 super. This when people were waxing lyrical about Seymour's Fluorinert "Bubbles". Heady days back then--you almost needed a program to keep track of the various projects. --Chuck

On 3/9/23 18:24, steve shumaker via cctalk wrote: SBU-station buffer unit, but why not read about it in a contemporary article by Chuck Purcell? https://dl.acm.org/doi/pdf/10.1145/1500175.1500257 --Chuck

As to what a "station" looked like: https://i.pinimg.com/originals/15/6d/fa/156dfa0a3b573b6ff9ca074d62fb19a9.jpg Those things with CRT terminals on them are stations--they handle the various I/O tasks. Basically, 16 bit minicomputers. The photo might be the installation at CDC ADL, from the low ceiling and cramped space. During the OPEC oil embargo, I made myself comfortable with a pillow borrowed from my room at the Ramada and a good book nestled between the SBUs. It was probably the warmest place for miles. The offices at ARHOPS, by contrast, had ice on the inside of the windows... Back then, in Sunnyvale, you had three choices if you were doing OS development. You could turn in your build materials to the STAR-1Bs at SVLOPS and hope that an all-night (the 1B ran at 1/100 the speed of the 100) session didn't end in a system crash. You could finagle some CE time at Lawrence Livermore, which was far from a sure thing (one of the reasons for having a DOE "Q" clearance). Or you could hop the "noon balloon" out of San Jose to the Twin Cities and use the STAR at ADL. If it was wintertime, my department in Sunnyvale had a "community parka" for those unfortunates visiting the land of ice sports. --Chuck

Mainframe - Minicomputer = RAS and order magnitude better I/O On Fri, Mar 10, 2023 at 7:42 AM Paul Koning via cctalk < cctalk(a)classiccmp.org&gt; wrote: -- Lee Courtney +1-650-704-3934 cell