4 May
2025
4 May
'25
10:21 p.m.
On May 4, 2025, at 4:05 PM, Steve Lewis via cctalk
<cctalk(a)classiccmp.org> wrote:
The IBM5100 also uses the term "microcode" - but I'm not sure if that term
pre-1975 means the same as what, say, Intel used it for around the x86?
I've seen a glimpse into the syntax of the x86 microcode. In the IBM
5100's case, its CPU is distributed across 14 or so SLT chips - so I never
fully understood how it implements its PALM instruction set. I know the
two large IC on that process are two 64-byte memory things (dunno if
categorized as SRAM or DRAM, or neither), mapped to the first 128 bytes of
system RAM (so a high speed pass through, where that 128 bytes correspond
to the registers used by each of the 4 interrupt levels). That PALM
processor was developed right around the time of the Intel 4004 (late '71 /
mid '72), and stout enough to run a version of APL about a year later (I
see Intel made a version of FORTRAN for the 8008, or at least a claim for
it in the Intertec brochures).
Anyway, all I mean is, in early 70s did "microcode" just mean
instruction-set, and that changed a few years later? Or did microcode
always mean some kind of "more primitive sequence" used to construct into
an instruction set?
The latter, as far as I know. And in "horizontal microcode" you have a rather
wide microcode instruction word with a bunch of fields, each of which encodes a portion of
what the machine is doing for a particular cycle. The microcode and the microengine may
well be specialized for a particular instruction set, as opposed to the "general
purpose" microcode that lets you pick the "macro" instruction set fairly
broadly. For example, with the possible exception of the PDP-11/60 I suspect that PDP-11
microengines do PDP-11 instruction set execution nicely, but wouldn't be all that
effective with other ISPs. The 11/60 is a bit different, at least I know it was used to
implement PDP-8 execution at speeds higher than that of "real" PDP-8 machines.
paul