[cctalk] Re: mainframe vs mini

On interrupt coalescing (mentioned under "performance techniques"), an early -- perhaps first -- implementation is in the Electrologica X8. It uses queues guarded by semaphores to communicate with the I/O coprocessor CHARON, and the interrupts delivered in response are also controlled by a semaphore. The initial count of that semaphore specifies how many I/O operations to complete before an interrupt is done. Its semaphores are constructed around a hardware primitive that adds a register to memory and delivers the result both to that memory location and to the register, interlocked via a read/modify/write core memory cycle. paul