23 Jan
2023
23 Jan
'23
2:13 p.m.
On 1/23/2023 1:21 PM, Mike Katz wrote:
Thank you for clearing up the CoCo 3, I never had one. I know the
MC6887 could address and handle the refresh for 96K.
I'll have to read up more on SAM. I know it can have 96 memory, but I
thought is was 64kB RAM and 32kB ROM.
OS9 Level II was designed by Motorola and Microware and made full use
of the capabilities of the 6809 architecture. With simple Dynamic
Address Translation 1MB of extended address space was available.
The CoCo 3 could only do 512kB, due to the translation granularity being
8kB and the GIME DAT only have 6 bits. But, back in the day and today,
there are solutions to extend that to 8 bits per translation, which
brings up to 2MB. CoCo 3 based L2 OS9 only supports up to 2MB
natively. There is a few > 2MB options, but OS9 can currently only use
the >2MB as a RAM disk.
Jim
On 1/23/2023 12:11 PM, Jim Brain via cctalk wrote:
I stand corrected:
"Switching the SAM into 1.8 MHz operation gives the CPU the time
ordinarily used by the VDG and refresh. As such, the display shows
garbage; this mode was seldom used. However, an unusual mode available
by the SAM is called the Address Dependent mode, where ROM reads (since
they do not use the DRAM) occur at 1.8 MHz but regular RAM access occurs
at .89 MHz. In effect, since the BASIC interpreter runs from ROM,
putting the machine in this mode would nearly double the performance of
a BASIC program while maintaining video display and DRAM refresh. Of
course, this would throw off the software timing loops and I/O
operations would be affected. Despite this, however, the "high speed
POKE" was used by many BASIC programs even though it overclocked the
hardware, which was only rated for 1 MHz operation. "
Note that the CC3 had a speedup poke that was different and did in fact
speed the entire system with video intact.
On 1/23/2023 11:53 AM, Mike Katz via cctalk
wrote:
I don't recall if that was the CoCo 2 or CoCo 3 but the system could
handle 1.8MHz (with a MC68B08E CPU). The memory had to be 2MHz to
handle the alternate cycling.
The 6883 SAM was the "glue" that provided all of the timing and
address decoding for the entire system. To reduce flicker the 6847
and 6809E memory accesses were alternate cycled. This means that
they used opposite edges of the Phase 1 clock to access memory.
However, this meant running the system at .8949 MHz. The SAM had
the ability to run the CPU at twice that speed but this resulted in
the video being disabled.
Are you sure about that? The system could be sped up, which involved
not refreshing DRAM, but all of the support ICs and the DRAMs are
1MHz, so I don't think 2MHz was possible on the CoCo, at least.
The straight MC6809 (non E version) used a more forgiving quadrature
clock but could not be alternate cycled.
Actually, the 6809E is the Q/E clock version. The 6809(non e) is the
crystal based one.