21 Jun
2024
21 Jun
'24
9:17 a.m.
On Thu, Jun 13, 2024 at 10:15 AM CAREY SCHUG via cctalk <
cctalk(a)classiccmp.org> wrote:
I think I recall an early processor that did out of
order execution,
without checking, meaning you could have
add xxx to accumulator
store accumulator in zzz
The Intel i860 (unrelated to x86, i960, and the much more recent "i860
chipset") has a pipeline that is more exposed to the programmer than in
most RISC processors. It has interlocks so that having an instruction write
a register followed by an instruction that reads that register will incur a
pipeline delay. However, the floating point unit offers most operations in
either a scalar mode or a pipelined mode. In pipelined mode, the pipeline
is much more visible to the programmer. The destination of a pipelined-mode
FP operation is where the result of the FP operation two instructions
previous is strored, not the result of the current operation, and there is
no interlock. A pipelined FP operation immediately followed by a store will
not store the result of that operation. Needless to say, programming in
pipelined FP mode is challenging, but it's the way to get the highest FP
performance out of the i960. Math libraries used hand-written code to do
that, but I don't think any of the i960 compilers were smart enough to do
it for you.