On 4/22/24 11:46, Paul Koning wrote:
Probably not. Cycle accurate simulation is very hard. It's only rarely been done
for any CPU, and if done it tends to be incredibly slow. I remember once using a MIPS
cycle-accurate simulator (for the SB-1, the core inside the SB-1250, later called
BCM-12500). It was needed because the L2 cache flush code could not be debugged any other
way, but it was very slow indeed. Almost as bad as running the CPU logic model in a
Verilog or VHDL simulator. I don't remember the numbers but it probably was only a
few thousand instructions per second.
Then again, the Z80 isn't a very sophisticated chip. No cache,
pipelining, speculative execution, etc. A cheap 32 bit MCU, running at
400 MHz might be able to pull it off pretty well.
But then again, there are FPGA cores for the Z80, etc.
I'd like to see a Z80 implemented with UV-201 vacuum tubes... :)
--Chuck