22 Apr
2024
22 Apr
'24
4:51 p.m.
On Mon, Apr 22, 2024 at 9:18 AM Chuck Guzis via cctalk
<cctalk(a)classiccmp.org> wrote:
On 4/22/24 08:36, Lamar Owen via cctalk wrote:
All sorts of interesting details are covered in several of Ken
Shirriff's blog posts.
Here are a few:
The Z-80 has a 4-bit ALU. Here's how it works.
https://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-how-it.html
Reverse-engineering the Z-80: the silicon for two interesting gates explained
https://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html
The Z-80's 16-bit increment/decrement circuit reverse engineered
https://www.righto.com/2013/11/the-z-80s-16-bit-incrementdecrement.html
Why the Z-80's data pins are scrambled
https://www.righto.com/2014/09/why-z-80s-data-pins-are-scrambled.html
Die real estate forced the design to do without a
full 8-bit ALU. When
you have a 4-bit ALU, and you are doing 16-bit math, you will need 4
cycles through the ALU.
I don't know if this applies to the Z80, but on the 8080, 16-bit
increment/decrement is handled by a separate increment block (also used
to advance the P-counter and stack operations). Probably one of the
reasons that INX/DCX doesn't set any flags.