13 Jun
2024
13 Jun
'24
3:28 p.m.
On Thu, 13 Jun 2024, Paul Koning via cctalk wrote:
MIPS, perhaps? It has "delay slots". The
one that remains is the
branch delay slots, which in modern designs is presumably merely an
annoying crock that requires extra pain to implement but is actually
required because it changes the meaning of the code. There also used to
be load (?) delay slots, which sounds like what you're describing.
Yes, MIPS I load delay slots. Gone by the MIPS II/III ISAs, though
coprocessor move delay slots remained (e.g. for moving data between the
GPRs and the FPRs), having only been removed with the MIPS IV ISA. For
the remaining missing interlocks there are now instructions in the ISA to
clear the hazards resulting (i.e. possibly stall the pipeline) explicitly,
so there is no need to count instructions anymore.
Also various extensions and revisions of the ISA have added the so called
compact branches that have no delay slot, starting with the MIPS16e ASE.
And then the microMIPSr6 ISA encoding only has compact branches available.
That was ancient history by the time I started working
on MIPS machines,
fortunately.
MIPS I cores and variations were still around by late 1990s in embedded
use, and of course the GNU toolchain continues to support all the arcana
to this day, as do community-maintained OSes.
Maciej