4 May
2025
4 May
'25
7:57 p.m.
On May 4, 2025, at 1:36 PM, Steve Lewis via cctalk
<cctalk(a)classiccmp.org> wrote:
I get that, that a general purpose processor with a particular instruction
set can be made up from TTLs (or vacuum tubes, or water sleuths, or metal
gears, etc), and am familiar with the Datapoint (and it always was odd to
me that Wang called their model the 2200 like the Datapoint 2200; I know
both companies had various models).
But aren't modern ASICs essentially that idea of
software-implemented-in-hardware, mainly for dedicated performance? If
you had "perfected" your software and accepted no code change was
necessary, the coding did exactly whatever it is you needed to do, you can
then commit that to some combination of hardware-logic-gate-stuff (for the
sake of executing it wicked-fast, just as modern specialized crypto-ASICs
do) ?
Somewhat, but mostly not I think. The key point is that software is roughly sequential at
the conceptual level. Even with threading that's true for each thread. In the
hardware various things happen concurrently or even out of order, but the hardware does a
large amount of hard work to make that invisible. When it fails to get that right the
results can be interesting -- consider the Intel security bugs caused by speculative
execution.
An ASIC tends to do many things in parallel. When you look at a design language like VHDL
that's very obvious, and things look quite different from conventional programming
languages precisely for that reason. That means an ASIC implementation of a software
algorithm is likely to look quite different also, at least if it wants to take advantage
of all the potential speed-ups from casting things in silicon.
Consider DSP -- "Software defined radios" implement a DSP signal processing path
in software. And these have significant limitations because even very fast processors
struggle to do DSP operations at high frequency. In an FPGA you can go very much faster
because you can take each of the processing elements and implement them as a separate
block, and many of those can be futher pipelined. FPGAs aimed at doing DSP things will
often contain hundreds or even thousands of multipliers exactly for that reason.
paul