13 Mar
2025
13 Mar
'25
11:56 p.m.
On Mar 13, 2025, at 4:35 PM, ben via cctalk
<cctalk(a)classiccmp.org> wrote:
On 2025-03-13 1:36 p.m., Paul Koning via cctalk wrote:
To understand fully how the 6000 machines work, and to run code for those machines more
accurately than can be done on emulators. Also "because it can be done" -- the
same reason a lot of us do most of what we talk about on this list.
A while ago I used the VHDL model to understand a fairly well known but totally
undocumented detail of debugging peripheral processor programs from memory dumps (the only
tool available if the program gets stuck or lost). That detail: a system reboot will drop
a word of zero into each PP memory, usually at the place its program pointer pointed at
the time the boot reset happened. The data flow through memory, the processor guts, and
back to memory explains why, but you have to look really closely at low level block
diagram documentation to see it. On the other hand, it appears quite plainly when you run
the process on the VHDL model in a simulator.
paul
Depends on which one. RTL was 3.6 volts
positive, as far as I can remember. I actually have a keyboard that has some of those
devices in it. Yes, ECL is around 3 volts also but negative supply. And of course some
people designed systems with positive supplies but "negative" logic, in the
sense that ~0 volts is logic 1 while near-VCC is logic 0; the CDC 6000 series machines are
an example.
I was thinking of the PDP-8 there. 0 Volts logic 1 -3 volts logic 0.
FPGAs come in amazing sizes if you have
sufficient money. I hope some day to cram an entire CDC 6600 into an FPGA. The main
problem with this isn't FPGA sizes (by today's standards, an upper-midrange FPGA
can do the job, memory included) but rather the creation of an accurate model given the
bizarre and hairy timing of that machine. I have a gate level model, but it doesn't
work yet because of those issues.
What would the purpose of said computer be?
Might be better off with a clean 64 bit design and 16 bit bitslices.