10 Jun
2024
10 Jun
'24
4:18 p.m.
On 10/06/2024 05:54, dwight via cctalk wrote:
No one is mentioning multiple processors on a single
die and cache that is bigger than most systems of that times complete RAM.
Clock speed was dealt with clever register reassignment, pipelining and prediction.
Dwight
Pipelining has always been a double edged sword. Splitting the
instruction cycle into smaller, faster chunks that can run
simultaneously is a great idea, but if the actual instruction execution
speed gets longer, failed branch predictions and subsequent pipeline
flushes can truly bog down the real-life IPS. This is ultimately what
led the NetBurst architecture to be the dead-end it became.
DEC came across another issue with the PDP-11 vs the VAX. Although the
pipelined architecture of the VAX was much faster than the PDP-11, the
actual time for a single instruction cycle was much increased, which led
to customers requiring real-time operation to stick with the PDP-11, as
it was much quicker in those operations. This, along with it's large
software back-catalog and established platform led to the PDP-11
outliving it's successor. Josh Rice