6 Sep
2023
6 Sep
'23
7:48 p.m.
On Sep 6, 2023, at 3:32 PM, Jon Elson via cctalk
<cctalk(a)classiccmp.org> wrote:
On 9/6/23 14:00, Mike Katz via cctalk wrote:
Even then it increments by 2, by special exception. So 112700, 1 (movb #1,r0) fetches the
instruction and increments PC by 2, then fetches the word where the PC points and
increments by 2, not 1, again.
The weird case of the 11/05 is because the general registers are assigned addresses 177700
through 177707 for R0 through PC, so R1 is at 177701 even though it's a word wide. On
most models those addresses only work from the operator console, but on the 11/05 they are
also visible from the program. And by special microcode hack ("just because they
could", says ABC) if the PC is in that range it increments by 1.
paul
Paul,
I'm not an 11 expert but don't most instruction fetches (or the last clock phase
on an instruction) cause the pc to increment by one?
PDP-11 instructions are
16-bit. Since memory is byte-addressed, the instruction counter should normally increment
by 2, except where immediate operands are used.