15 Jun
2024
15 Jun
'24
9:14 a.m.
On 6/13/24 09:33, Adrian Godwin via cctalk wrote:
I may be wrong, but wasn't that a feature of early
RISC, possibly the Sparc
? You were compiling to microcode rather than CISC assembler, so you got to
think about pipelining in the instruction stream. Just about feasible in
assembler but perfectly sensible if the compiler was doing the work.
PS-RISC has a "delay slot" after a branch and the instruction there
will be executed before the branch target is reached for a taken
branch.
You can do fun things like put a branch in the delay slot of another
branch and when both are taken, you end up executing a single
instruction at the target of the delay slot branch before resuming at
the target of the original branch.
PA-RISC implements PC as PCQ, a two entry queue containing the current
instruction address and the "following instruction address" which get
manipulated by the branches to create this behavior.