31 Oct
2024
31 Oct
'24
12:25 p.m.
On 10/31/24 10:39, Paul Koning wrote:
I could imagine it in PPs, also in 6400 machines since
they don't have an "instruction stack" so instruction fetches would go to
memory. For all of those you'd end up hammmering a single memory cell at high speed,
and each time you do that you get a read and a write cycle, both of which inject some
energy into the cores in question.
http://www.bitsavers.org/pdf/cdc/cyber/cyber_70/60258200C_7600_RefMan_Feb71…,
PDF page 90 "Duty Cycle Integrator" for SCM in the CPU was the fix for
the problem. You won't find it described in the very early 7600
hardware manuals.
At first, I wondered if it might be a PPU thing, as the 7600 PPUs
operate independently (no "barrel"), but the situation would be easy to
avoid, since the casual user doesn't write PPU code. "Don't do that"
would be sufficient.
At any rate, the 7600 was a marvel of complexity when compared with its
earlier 6000-series relatives. I remember marveling at the SCOPE 2
design documents and how very different they were from the 6000
operating system implementation.
--Chuck