[cctalk] Re: early microprocessor limited pipelining [was: Intel 8086 - 46 yrs. ago]

Pn Thu, Jun 13, 2024 at 11:57 AM Paul Koning via cctalk < cctalk(a)classiccmp.org&gt; wrote: MIPS has delay slots for branches (two for Standord MIPS, one for commercial MIPS), but no delay slots for ALU operations. All MIPS implementations either interlocked the pipeline to avoid a race when an instruction that writes a register is followed by one that reads that register, or (more commonly after the early RISC days) has feed-forward in the pipeline.