[cctalk] Re: IBM 5100 emulation

I've poked around inside the 5100 some years ago, but most of my information came from the Maintenance Information Manual, and I only verified a little of it relating to the executable ROS. The executable ROS is split between a half card in slot H2, which is required for all 5100 models, and an APL-only executable ROS half card in slot H4. The most significant address bit (SAB 0) selects between the two. The BASIC/IO/Diagnostic executable ROS starts at address 0000, and the APL executable ROS starts at 8000. It appears that the BASIC/IO/Diagnostic executable ROS occupies most or all of the address space allocated to it, 0000..7fff space (32KB). The non-executable ROS cards are: slot E2 (full size): ROS control, and common and language ROS, all models - it appears that this is addressed ABOVE (at higher addresses than) the BASIC ROS slot C4 (half card): BASIC ROS slots C2, D2, D4 (half cards): APL ROS The MIM shows the non-executable ROS as divided into banks of 30720 bytes (0x7800). I can believe that the amounts of memory on a particular card might be related to that, e.g., 15 chips of 2KB each, but the decode on the ROS Control card is shown as decoding consecutive ranges of that size, rather than e.g. units of 0x8000. Two decodes go to each non-executable ROS card, so it appears that the 0x7800 bytes of a bank are not actually implemented on a single card. Something bizarre seems to be going on, or possibly the documentation isn't 100% accurate. I think the non-executable ROS is selected slightly differently than in the 5110. The non-executable ROS is device address 1. The MIM says in one place that in a control operation, data bit 4 selects common and BASIC, while data bit 5 selects APL. Bits 4 and 5 come from bits 12 and 13 of the control microinstuction. I'm not convinced that the logic diagrams match that description.