[cctalk] early microprocessor limited pipelining [was: Intel 8086 - 46 yrs. ago]

I think I recall an early processor that did out of order execution, without checking, meaning you could have add xxx to accumulator store accumulator in zzz and the store could happen before the add if there weren't sufficient instructions between the two. I *DON'T* recall if it was designed this way or a defect in the chip design. I think it was intended to be a real-time process control cpu and speed was more important than ease of programming. There was a assembler/compiler that warned of this case, afaik