27 Feb
2024
27 Feb
'24
2:09 p.m.
On Feb 27, 2024, at 4:49 PM, CAREY SCHUG via cctalk
<cctalk(a)classiccmp.org> wrote:
Religion warning: I was a mainframer. Since at any practical budget, they can only be
emulated,
Depends on your definition of emulated. Is an FPGA version merely an
"emulation"? You might say yes if it's a functional model. Arguably no, if
it's a gate level model.
Suppose you had schematics of, say, a KA-10. You could turn those gates into VHDL or
Verilog, and that should deliver an exact replica of the original machine, bug for bug
compatible. That assumes the timing quirks are manageable, which for most machines should
be true. (It isn't for a CDC 6600.)
paul