[cctalk] Re: Delay slots, was: Re: Re: early microprocessor limited pipelining [was: Intel 8086 - 46 yrs. ago]

Probably, because divide is inherently an interative operation, and usually is implemented to produce one bit of result per cycle. A notable exception is the CDC 6600, which throws a whole lot of logic at the problem to produce two bits of result per cycle. The usual divide amounts to a trial subtraction and shift; the 6600 implementation does THREE trial subtractions concurrently. Not cheap when you're using discrete transistor logic. Multiply is an entirely different matter, that can be done in few cycles if you throw enough logic at the problem. Signal processors are an extreme example of this because multiply/add sequences are the essence of what they need to do. This is also why Alpha omitted divide entirely and made programs do multiply by the reciprocal instead. The best argument for doing interlocking in the hardware isn't that it's hard for software to get right. Code generators can do it and that's a one time effort. But the required are often dependent on variables that are not known at compile time, for example load/store delays, or branches taken/not taken. Run time interlocks deal with the actual conflicts as they occur, while compiler or programmer conflict avoidance has to use the worst case scenarios. paul