17 Feb
2025
17 Feb
'25
12:58 p.m.
On 2/17/25 11:38, Paul Koning wrote:
Yes, though it's possible to enable such things
with condition code machines if the setting of the condition code is selective. The
Electrologica machines have this: there is an instruction modifier bit that tells the
machine to update the condition flag based on result zero, result positive, or a third
option that I never remember -- or to leave it untouched. Subroutine calls save the flag
and the return can restore it if you want, or not if you don't. Finally, almost all
instructions can be conditional on the flag if you want, either "execute if flag
set" or "execute if flag clear" or unconditional. The EL-X1 Wikipedia
article shows an example.
Didn'r know about the EL one, thanks.
I don't know that one, but there is the famous
OTOD -- convert a 60-bit value to a 20 digit octal string. I did a variation on that (not
quite as slick) to convert a 60-bit value to a 15 digit hex string.
Yes, I recall that one.
Interesting. I worked on a 6500 so a lot of
optimizations were not relevant, but I spent a while studying code in NOS to learn how to
do it. One thing that did matter was shuffling instructions around to avoid NOP padding.
I once had a piece of code that was subject to hard real time constraints -- which I did
not know -- so when I broke it I had to revise it to get rid of all the NOPs. Then it was
fast enough again.
I seem to remember that using non-zero registers in the no-op (46000)
instruction could affect the timing. It was a long time ago and before
the CMU.
Really? I never heard of anyone who ran with CEJ
disabled -- why would you want to do that?
I assume that CE MACE had some tests that required it to be disabled.
At least I recall taking the system after CE time and having to remember
to check the CEJ/MEJ switch as well as the deadstart code switches.
Greg Mansfield might recall details, but I don't know if he's still
around--he'd be in advanced golden years now.
Indeed, though I sure would like to know how to make
the timing work. If you do what's documented in the schematics (in a VHDL model) it
doesn't work.
My section manager from the 70s, Mike Miller, had the job as a
wet-behind-the-ears EE fresh from UM had the job of measuring the
backplane loops to which Seymour had attacked a tag that said "TUNE".
One doesn't normally think of wire length being critical to operation,
but apparently it was on the 6600. I don't know if the schematics show
that.
One architecture not actively discussed even donkey's years back was the
7600. You couldn't run a 6000-series deadstart tape on it, because of
substantial architectural differences. The PPUs were assigned buffer
areas in SCM and couldn't stray out of them, so a PPU-oriented operating
system wasn't possible. 7000 SCOPE used the idea of nested field
lengths to implement the OS. So you had Job Supervisor, Buffer Manager,
Record Manager...and so on until the user program on the innermost FL,
something like one of those Russian matryoshka dolls . Apparently, it
was very inefficient in practice, particularly given the relatively
small amount of SCM.
--Chuck