30 Jun
2023
30 Jun
'23
3:02 a.m.
That's a good point, though like you I don't know of anything that ever
tried to take advantage of that theory (though I wouldn't have been paying
enough attention at the time to confidently comment, so...). Since it's
not 'common knowledge' that it was done, I'd surmise either 1) the reality
is harder than the theory, or 2) it made more sense to wait for Intel chips
with less limitations, which seemed to me to be what was going on at the
time. But certainly an interesting 'what if'.
KJ
On Fri, Jun 23, 2023 at 3:37 AM Christian Corti via cctalk <
cctalk(a)classiccmp.org> wrote:
On Fri, 23 Jun 2023, Ken Seefried wrote:
Didn't see anyone mention it, but one should
recall that the whole memory
space on the 8088/8086 was 1M, so a 'limit' (whatever kind) of 640K
wasn't
Well, it only has 20 address bits. But it can address much more memory
because it has additional information on some status pins about what
segment register is used for adressing. So in theory, you could have one
separate 1Mb of memory for each possible segment register. Or at least you
could easily separate the stack from the other memory.
Anyone here know of a design that actually made use of this?
Christian