On Apr 22, 2024, at 3:31 PM, ben via cctalk
<cctalk(a)classiccmp.org> wrote:
One other factor is that RISC machines rely on
simple operations >carefully arranged by optimizing compilers (or, in some cases,
>skillful programmers). A multi-step operation can be encoded in a >sequence of
RISC operations run through an optimizing scheduler more >effectively than the
equivalent sequence of steps inside the
micro-engine of a CISC processor.
Lets call them LOAD/STORE architectures.
Classic cpu designs like the PDP-1, might be better called RISC.
Um, no. Load-store machines like the PDP-1, or many other machines of that era, have
instructions where typically one operand is a register and the other is a memory location.
That means arithmetic operations necessarily include a memory reference, implying a
memory wait.
A key part of RISC is arithmetic on registers only, and enough registers so you can
schedule the loads and stores to run concurrently with other arithmetic operations. The
CDC 6600 is the pioneering example. A very simple scenario would be a memory move loop,
where you'd issue two loads to two different registers, then two register-register
move operations that use different functional units, followed by two store operations from
two different registers. (The move operations because the 6600 would do loads to one set
of registers and stores from a different set.) Keeping two memory operations in flight
concurrently made quite a difference.
In COMPASS:
MORE SA1 A1+B2 (B2 = 2)
SA2 A2+B2
BX6 X1
LX7 X2
SB3 B3-2
SA6 A6+B2
SA7 A7+B2
PL b3,MORE
paul