[cctalk] Re: Z80 vs other microprocessors of the time.

Cycle accurate emulation becomes impossible in the following circumstances: * Branch prediction and pipelining can cause out of order execution and the execution path become data dependent. * Cache memory.  It can be very difficult to predict a cache flush or cache miss or cache look aside buffer hit * Memory management can inject wait states and cause other cycle counting issues * Peripherals can inject unpredictable wait states * Multi-core processors because you don't necessarily know what core is doing what and possibly one core waiting on another core. * DMA can cause some CPUs to pause because the bus is busy doing DMA transfers (not all processors have this as an issue). * Some CPUs shut down clocks and peripherals if they are not used and they take time to re-start. * Any code that waits for some kind of external input.