14 Oct
2025
14 Oct
'25
5 p.m.
On 2025Oct 13,, at 2:13 PM, Rob Jarratt <robert.jarratt(a)ntlworld.com> wrote:
There’s some confusion here somewhere.
Those input V's would imply the comp. output should be loZ to Vsupply– pin, around
–12V; not hiZ, +7.5V.
The output for these comparators is an open-collector NPN transistor with E on the
Vsupply– pin.
Behaviour is:
inputs V output output output
relation trans’r Z logical
===== ===== ==== ====
+in > –in OFF hiZ 1
+in < –in ON loZ-to-Vsup– 0
Where Vin are a signed voltage.
So for the input V's you mention, what should be occurring is:
E1a.+in = +6.3V
E1a.–in = +10.4V (these would be saying
‘power-is-good')
==> +in < –in
==> E1a.outTran = ON
==> E1a.outV = –12V ~ (because E1.Vsupply– = –12.9V ~, per your prior
measurement)
==> JFET.G < 0V (negative by some number of volts)
==> AC-OK = hi-Z = logic.1 = +V with pull-up R.
I will locate this diode and measure it and also check the 7812, but it might be a
couple of days before I get time to do this.
Note the 5.1V comes from the DRM and it’s conceivable DEC adjusted the design and put a
6.2V zener in there without updating the DRM.
IMO it’s something that should be sorted out as Vz is used for a bunch of control refs,
though not the main Regulation ref.
Ideally the diode type would be visible.
On 2025Oct
12,, at 3:28 PM, Rob Jarratt <robert.jarratt(a)ntlworld.com> wrote:
…
No, its about 7.5V. The comparator +ve input is 6.3V and the -ve input is 10.4V, making
the comparator output high impedance. I measure about +4mV on the gate of the JFET. I
think this means the JFET will be conducting and so pulling the AC OK H down to 0V, which
is what I see when I include a pull up resistor on the AC OK H output. What you write
below would seem to confirm this. I measured AC OK by adding a pull up resistor,
but if I am honest, I
forgot about this in my latest measurements. I have also looked at
Power OK, knowing that AC OK needs a pull up resistor, and it is
logically false, so it is definitely saying the power is not OK.
What is ‘logically false’? 0V or –V? Vstart is 11.3V and Vz is 6.4V. I have not been able
to find where Vz
comes from on the schematic either, if I elaborate the KiCad
schematics further I will try to find its source.
TDS = Tony’s schematic
DRM = DEC rainbow manual per Wayne’s ref.
Vz is in the lower left corner of TDS.pdf.5.
Vz is apparently “V PR” in DRM and should be 5.1V [DRM.pdf.261-7.4.2.1].
Which is to say the zener there is some 5.1V type.
6.4V is rather high.
I would suggest finding that zener on the board and measure right across it.