12 May
2023
12 May
'23
5:05 a.m.
On May 11, 2023, at 10:41 PM, Cameron Kaiser via
cctalk <cctalk(a)classiccmp.org> wrote:
Yes, if they are small RAM chips. For example, in a 1k DRAM chip (and perhaps in slightly
larger sizes too) the row size could be 32, which means that the failure of one row on one
RAM chip would cause the failure of an aligned 32 byte range.
paul
I thought about this, but the KIM is a pretty
simple system. The only memory
mapped device in that range (really, on the entire unit) are the RIOTs, and
their RAM at $1780 is fine and does not echo.
The KIM only does address decoding for 8K and echoes the rest, so the same
fault is mapped at $2280, $4280, etc. I would think this would still suggest
data is the problem.
I suppose I could randomly replace the RAM and see what changes but again it
seems weird to have a fault so neatly aligned and only in a specific range.
...
and the high nybble is OK). Now that sounds more like a bad RAM chip, but why
would it be *just* those addresses? Does that sound like a plausible failure mode?