8 Aug
2025
8 Aug
'25
10:30 a.m.
On 2025-08-08 10:54 a.m., Maciej W. Rozycki via cctalk wrote:
On Thu, 7 Aug 2025, Paul Koning wrote:
The key concepts clearly borrowed from the MIPS ISA
were: a hardwired
zero register and the dependency on that for the completeness of the ALU
operations provided, the lack of condition codes and the use of general
registers instead for conditional branches..
Funny how most classic computers, did the same thing.
It was called skip on condition.
With out the advance of large fast paged DRAM's RISC would
never got out the Door.
Maciej
Why does it seem we have new RISC
version every other monthand the INTEL
X86 err PDP8 keeps going and going. :)