8 Aug
2025
8 Aug
'25
1:23 p.m.
On Aug 8, 2025, at 2:14 PM, ben
<bfranchuk(a)jetnet.ab.ca> wrote:
On 2025-08-08 11:52 a.m., Paul Koning wrote:
You should spend some time looking at old machine architectures, because what you say is
very 21st century centric. An excellent intro is "Design of a computer - the
Control Data 6600" by J. E. Thornton. Available on Bitsavers
https://bitsavers.org/pdf/cdc/cyber/books/DesignOfAComputer_CDC6600.pdf or you can get the
hardcover printed book.
It's a great machine to study because it does an amazing job of matching up parts of
the design to wring the most performance out of the available components. To pick one
example: the primary clock period is 100 ns, and most operations take only a few cycles.
A new instruction can start every 100 ns, best case. The memory system is designed so it
can push data around at that speed. Process context switch requires 16 word read/write
operations, and that process is skillfully pipelined so it normally runs in 16 consecutive
cycles, spread over the memory banks (16 banks in the minimal system, 32 in the full
memory config). And so on.
It doesn't require SIMMs or a "cpu chip set" to go fast.
paul
The 6600 max memory was 128k 60-bit words, which
for those days was admittedly quite large. No VM, though it did support relocation (base
address and field length, similar to the DEC KA10). Large RAM is nice but I don't see
what it has to do with RISC.
It was DRAM in SIMM packaging, that let you have a
fast memory bus off the cpu chip set.