22 Sep
2023
22 Sep
'23
10:51 p.m.
On 9/22/2023 4:45 PM, ben via cctalk wrote:
On 2023-09-22 3:16 p.m., Mike Katz via cctalk wrote:
As an alternative, perhaps consider basing a design on the PDP-11
QBone/UniBONE boards, with bus interface chips to handle the 5V UNIBUS
signalling and a Beagle Bone with it's attached processors (PRU) for the
bus interface. That would allow a lot of work to be done in plain old
C/C++/Whatever, and the board could serve as a debug board, peripheral
emulator, whatever based on whatever software was loaded onto BB.
Also, if one would want to do logic in an FPGA, VHDL and Verilog aren't
*that* hard to learn if one has a background in hardware. Some resources
include:
Logic and Computer Design Fundamentals, Mano/Kime, Prentice Hall
Digital Design using Digilent FPGA Boards (There are VHDL and Verilog
editions)
Advanced Digital Design Using Digilent FPGA Boards
Even if one is not using Digitlent boards, the examples given for
various typical uses cases for things are helpful (counters, state
machines, multiplexers, selectors etc. etc.)
JRJ
Martin,
The debug board will need to have the following functionality:
1. Read and write to/from memory when the CPU is running using one
cycle data break (DEC's version of DMA for the PDP-8). Single Cycle
DMA requires some interesting signaling, including putting the
priority on the data bus during part of the cycle.
2. Read and write to/from memory when the CPU is halted using front
panel emulation (something totally different than one cycle data
break unfortunately)
3. Handle 4 breakpoints (based on address, data, R/W and count) and
signal the cpu to stop. I don't know, yet, if there will be enough
time in the CPU's instruction cycle to top the CPU before the fetch
of the next instruction. If this cannot be done in hardware than a
much more crude break point system can be done in software.
4. There are 96 active signals on the PDP-8/E's Omnibus. I expect to
need most or all of them for this project.
5. The Omnibus is an open drain, active low bus where +2.7V to +4.5V is
a zero and -0.5 to +0.4V is a one. I don't necessarily need a 5V
tolerant gate array but what ever I use to interface to the bus will
need to be.
A full description of the Omnibus can be found here:
https://bitsavers.org/pdf/dec/standards/EL-00157_00_A_DEC_STD_157_OMNIBUS_S…
Coding the break point system in some kind of parallel C like
language seems way easier to me than to write this in gates. I don't
have a clue how to design the count registers.
I need to get #'s 1 and 2 working first and then I can dive into #3.
Thanks.
Hexadecimal displays til311, (pulled DIS1417's) can be found on ebay
for about $5 not counting shipping. This way you have easy to read hex
or octal numbers.