[cctalk] Re: Last Buy notification for Z80 (Z84C00 Product line)

On 2024-04-21 5:26 p.m., Chuck Guzis via cctalk wrote: Thru the hole and 5 volt and cheap and easy to find ( at one time ) and low edge rates , are important for me as I have kitchen table kind of projects. Before you say use XXX , I don't have the skills or the tools to layout and debug high tech boards or parts. I am very unlucky with FPGA stuff. My current bit slice computer design has some sort of dynamic problem, as only some instructions will run or read correctly. Halt and STOP don't work. Front panel works mostly. I need to rethink a whole new design,as something I can build and test and find parts for. The goal is a 20 bit word length computer, with 10 bit bytes,bit slices, Compact flash , UART's and blinking light front panel. I may run in emulation, until I can get hardware built and debugged but I have not found a host computer I like. So if any one wishes to take on this project, feel free using modern parts. Ben. * april 21 2024 sdc 1 Small Data Processor 1 .815 uS CYCLE TIME - BYTE BASED COMPUTER - INDEX REG'S - REGISTER OPS - CARRY BIT - AUTO/INDEX - LOGIC OPERATIONS - HEX FRONT PANEL MM 00 0 0 10 2 1 01 WRD wrd 11 SEX sx 5 4 3 2 1 +----+----+----+----+----+ |OOOO:AAAA|XXXX:B321|+###| NORMAL +----+----+----+----+----+ OP TC 0 ST SUB ADD 1 ADD ADD RAMU Z SUB 2 SUB SUB RAMU C SBR 3 CAD SBR RAMU S OR 4 LD OR AND 5 OR OR RAMD Z BIT 6 AND AND RAMD C XOR 7 XOR XOR RAMD S XNR F C 0 0 0... CF F C 0 0 1... UART i = index , 0 # CCC COND TRAP (0) <- PC PC <- 2 ADR LOAD N 0 H/Z ST 1 A LD RAMU Z 2 B ADD RAMU C 3 C(carry)SUB RAMU S 4 G OR 5 X AND RAMD Z 6 Y XOR RAMD C 7 F/F JMP RAMD S REG C is CARRY IR PC CTL 0 0 TEST 0 1 DSP 1 0 HLT 1 1 DI/EI ----------------------- M1 = a/m1 M2 = b/m2 M3 = idx ---- M3,M2,M1 ST OP 0 0 0 CTL OP # 0 8 bits 0 0 1 HLT SCC 1 0 1 0 ST R+ OP R+ 2 0 1 1 JSV R+2 JCC R+2 3 1 0 0 - REG 4 1 0 1 - SFT 5 1 1 0 ST @R+ OP @R+ 6 1 1 1 ST X ST X 7 ----------------------- '/' LINE COMMENT 'star' BLOCK COMMENT BEGIN/END ONLY #OOO OCTAL PROGRAM COUNTER ______________ | KROMA.PLD | CP x---|1 24|---x Vcc AD7 x---|2 23|---x WR AD6 x---|3 22|---x PRA0 AD5 x---|4 21|---x PRA1 AD4 x---|5 20|---x PRA2 AD3 x---|6 19|---x PRA3 AD2 x---|7 18|---x PRA4 AD1 x---|8 17|---x PRA5 AD0 x---|9 16|---x PRA6 AUX x---|10 15|---x PRA7 x---|11 14|---x M3 GND x---|12 13|---x CLR_ |______________| [II8,sft,no,ld,ra,m2,m1,op,w,WR] ______________ | KROMB.PLD | CP x---|1 24|---x Vcc AD7 x---|2 23|---x BY AD6 x---|3 22|---x PRB0 AD5 x---|4 21|---x PRB1 AD4 x---|5 20|---x PRB2 AD3 x---|6 19|---x PRB3 AD2 x---|7 18|---x PRB4 AD1 x---|8 17|---x PRB5 AD0 x---|9 16|---x PRB6 aux x---|10 15|---x PRB7 x---|11 14|---x RD GND x---|12 13|---x CLR_ |______________| [RD,ctl,rx,rd',in',ir,mar,rd,b,BY] OCTAL CPU FOR 20 BITS ( RUN,ST)(M3,M2,M1) (cnt 3,2,1) 7 6 5 4 3 2 1 0 * / TIMES ARE IN MICROSECONDS #100 / IDLE PANEL ALL 4 CLOCKS 3.26 AC SW MAR NO PC CTL PC IR #110 / LOAD ADR AC LD WRD PC LD WRD MAR / DON'T CARE TERM AC PC IR #120 / READ MEM -> AC AC WRD LD PC 1 Y MAR AC RD IN AC LD WRD IR #130 / WRITE MEM -> AC AC WRD LD PC 1 Y MAR AC WR RD PC IR #200 / QUICK # 2 CLOCKS 1.63 PC 1 Y MAR AC OP SX BY RD IR #210 / SCC 3 CLOCKS 2.45 PC 1 Y MAR AC CTL AC LD IR RD PC / MET CC AC SX LD IR RD #220 / R+ 4 CLOCKS 3.26 IX SX Y MAR AC RD IN BY PC 1 Y MAR AC WRD OP IR RD #230 / JCC R+ 4 CLOCKS 3.26 CONDITION NOT MET IX 1 Y MAR AC CTL SX RD IN // ADD CONSTANT PC 1 Y MAR PC IR RD / MET CC SW NO MAR / 6 CLOCKS 5.4 CONDITION MET PC CTL / DISPLAY AC PC PC LD WRD MAR PC 1 IR RD #240 / REG OP 4 CLOCKS 2.26 IX NO WR IN / put IX on the bus PC 1 Y MAR AC OP WRD IR RD #250 / SHIFT x 1 2 CLOCKS 1.63 PC 1 Y MAR AC SFT IR RD #260 / MEM @ R+ 4 CLOCKS 3.26 IX SX Y MAR AC RD IN PC NO LD WRD MAR AC RD IN BY PC 1 Y MAR AC OP WRD IR RD #270 / MEM X 6 CLOCKS 4.89 PC 1 Y MAR PC RD IN IX NO WRD MAR AC RD IN BY PC 1 Y MAR AC OP WRD IR RD / store ops #300 / DI 2 CLOCKS 1.63 PC 1 Y MAR SW CTL RD IR #302 /TRAP / pc -> 0 pc = 1 PC LD NO MAR SW CTL RD WR PC LD 1 MAR PC RD IN PC LD WRD MAR PC 1 RD IR #310 / hlt 2 CLOCKS 1.63 PC 1 Y MAR IX CTL RD IR #320 / ST # 4 CLOCKS 3.26 IX SX Y MAR AC RD WR BY PC 1 Y MAR AC IR RD #330 JSV R+ 6 CLOCKS 4.89 IX 2 Y MAR PC RD IN AC 1 SUB MAR PC WR RD PC LD WRD MAR PC 1 IR RD #340 / NOP PC 1 Y MAR PC RD IR #350 / NOP PC 1 Y MAR AC IR RD #360 / ST @ R+ IX SX Y MAR AC RD IN PC NO LD WRD MAR AC RD WR BY PC MAR PC 1 IR RD #370 / MEM X 6 CLOCKS 4.89 PC 1 Y MAR AC RD IN IX NO WRD MAR AC RD WR BY PC 1 Y MAR PC IR RD / ALL DONE $