6 Sep
2023
6 Sep
'23
9:42 p.m.
On Sep 6, 2023, at 12:48 PM, Paul Koning via cctalk
<cctalk(a)classiccmp.org> wrote:
The weird case of the 11/05 is because the general registers are assigned addresses
177700 through 177707 for R0 through PC, so R1 is at 177701 even though it's a word
wide. On most models those addresses only work from the operator console, but on the
11/05 they are also visible from the program. And by special microcode hack ("just
because they could", says ABC) if the PC is in that range it increments by 1.
This was on the tip of my tongue because I was actually just debugging these very bits of
microcode on a GT40 (which Scott Swazey will be demoing at VCFMW running “Lunar Lander” if
it survives the journey there by car!)
The ALU B-leg input in the data paths on this CPU has a selection to generate constant +1.
In the usual cases, where the microcode needs +2 to be added to something, the additional
+1 comes from a microcode field bit and is added in at the ALU least-significant-bit-slice
carry input. There is additional circuitry to inhibit this carry input in special cases
like internal register address decodes, etc.
On our GT40, we had a microcode PROM failure which took out this very carry source bit.
Thus our GT40 PC was incrementing by just one _incorrectly_ in most cases where it should
have been incrementing by two. Quite a coincidence that your question came up soon after
dealing with this :-)
—FritzM.