7 Aug
2025
7 Aug
'25
11:10 a.m.
On Aug 6, 2025, at 6:29 PM, Maciej W. Rozycki via
cctalk <cctalk(a)classiccmp.org> wrote:
I believe the ancestry of Alpha is a bit different, given that it was DEC's third
generation RISC design, after the R&D one-off Titan (1982, see
https://bitsavers.org/pdf/dec/tech_reports/WRL-86-1.pdf) and the canceled PRISM (spring
1985, https://bitsavers.org/pdf/dec/prism/memos/850528_NONVAX.pdf which mentions Titan and
Berkeley but not MIPS as inspiration).
paul
...
Well, the very same year MIPS Computer Systems came up with the R2000, a
classic RISC design, featuring a(n almost) non-interlocked pipeline design
and with the same 4GiB paged virtual addressing capability and memory
protection also giving true multitasking. A processor architecture the
descendants of which live in millions of devices around the world, and
which inspired other architectures such as DEC Alpha or more recently
RISC-V.