29 Apr
2024
29 Apr
'24
1:25 p.m.
On Apr 29, 2024, at 1:59 AM, Steve Lewis via cctalk
<cctalk(a)classiccmp.org> wrote:
After learning more about the PALM processor in the IBM 5100, it has a
similarity to the 6502 in that the first 128 bytes of RAM is a "register
file." All its registers (R0 to R15, across 4 interrupt "layers") occupy
those first addresses. In addition, they are physically on the processor
itself (not in actual RAM).
That sort of thing goes way back. There is of course the PDP-6 and PDP-10 where the 16
registers alias to the low 16 memory locations. And the notion of registers per interrupt
level also appears in the Philips PR-8000, a 24 bit minicomputer from the 1960s aimed
(among other things) at industrial control applications. That sort of architecture makes
interrupt handling very efficient since it eliminates state saving. Unfortunately
there's very little documentation of that machine anywhere; the little I found is on
Bitsavers.
paul