13 Jun
2024
13 Jun
'24
12:33 p.m.
I may be wrong, but wasn't that a feature of early RISC, possibly the Sparc
? You were compiling to microcode rather than CISC assembler, so you got to
think about pipelining in the instruction stream. Just about feasible in
assembler but perfectly sensible if the compiler was doing the work.
To the limit of my knowledge, modern RISCs like ARM are much more like CISC
in that the pipelining is hidden, the name is used only to imply there's a
small and regular set of instruction codes.
On Thu, Jun 13, 2024 at 5:15 PM CAREY SCHUG via cctalk <
cctalk(a)classiccmp.org> wrote:
I think I recall an early processor that did out of
order execution,
without checking, meaning you could have
add xxx to accumulator
store accumulator in zzz
and the store could happen before the add if there weren't sufficient
instructions between the two.
I *DON'T* recall if it was designed this way or a defect in the chip
design.
I think it was intended to be a real-time process control cpu and speed
was more important than ease of programming. There was a
assembler/compiler that warned of this case, afaik