20 Feb
2025
20 Feb
'25
2:05 a.m.
On Wed, 19 Feb 2025, Paul Koning wrote:
An interesting variation of that is the Philips
PR8000, which has 8
general registers (well, one of the 8 is the PC, like on the PDP11)
though no stack. But actually it has 8 sets of 8 registers, one for
each processor priority level. So an interrupt automatically preserves
the previous registers, and the interrupt handler address is simply the
value found in R0 (the PC) for that level.
That is not unusual at all. The IBM PALM processor does this for example,
only that is has four sets of 16 registers. An interrupt just "shifts" the
register base address to $20 * interrupt level. There is no instruction
overhead at all. A "return from interrupt" merely clears the interrupt
request line for that level and the processor pops to the next-lower
active level, level 0 being the default.
Same with the MINCAL 523. The basic machine has eight run levels,
expandable to 64 levels. The default and lowest level is 0. You can change
the level either by an interrupt to that level (if not masked and no other
higher priority level is active) or by a processor instruction (making
kinds of subroutine calls effectively overhead-less; no need to save the
return address). The registers (also in memory space) are offset by 8, so
level 0 has its registers at addresses 0..7, level 1 at 8..15 and so on.
But, back to the topic, none of these machines have a hardware stack,
although on the MINCAL, you can write additional microcode and create new
instructions for what you like.
Christian