27 Feb
2024
27 Feb
'24
10:44 p.m.
Paul Koning wrote:
Suppose you had schematics of, say, a KA-10. You
could turn those
gates into VHDL or Verilog, and that should deliver an exact replica
of the original machine, bug for bug compatible. That assumes the
timing quirks are manageable
The mapping from asynchronous pulses, delay lines, etc, to VHDL or
Verilog isn't entirely straight forward. Still, it can be done, and
in the case of a KA10, it has. See https://github.com/aap/fpdpga