QSIC update

Noel Chiappa jnc at mercury.lcs.mit.edu
Sat Mar 5 07:01:57 CST 2016

    > So here's a quick update on where Dave Bridgham and I are with the
    > QSIC ... We have the first of two wire-wrap prototype QBUS motherboards
    > more or less (see below) done .. the hardware is 'mostly' working; most
    > of the work from here on out will be FPGA, etc, programming. There
    > _are_ a few additional QBUS lines used for bus master (DMA) and
    > interrupts which we haven't used yet, and one of the first things done
    > now is to get those two kind of bus cycles working
    > ...
    > With that in hand, we can do the first controller (RK11), using memory
    > in the FPGA to simulate a small disk. 

Well, Dave has made a big step down that road; he has DMA working (both the
bus arbitration cycle for DMA, as well as master-mode transfers to and from
QBUS slave memory).

He's now starting in on interrupt cycles; once those work, he effectively has
emulation of a minimal small RK (he already has all the registers, since he
needs them to control the DMA to and from the RAM disk). At that point I
should be able to test it by making it the swap drive on a Unix V6 load.


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