Mattis Lind mattislind at
Wed Apr 8 01:41:36 CDT 2020

Den ons 8 apr. 2020 kl 00:34 skrev Rob Jarratt via cctalk <
cctalk at>:

> > -----Original Message-----
> > From: cctalk <cctalk-bounces at> On Behalf Of Brent Hilpert
> via
> > cctalk
> > Sent: 06 April 2020 21:07
> > To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk at>
> > Subject: Re: VAXmate PSU
> >
> > On 2020-Apr-05, at 11:12 PM, Rob Jarratt wrote:
> > >>
> > >>> I have obtained a scope trace as you suggest. R32 is still lifted so
> > >>> the
> > >>> UC3842 is powered by the bench PSU, but I am using the full 240VAC
> > >>> (no variac). The channels are:
> > >>> 1.        Ch1. 555 timer.
> > >>> 2.        Ch2. D19 Anode
> > >>> 3.        Ch3. D19 Gate.
> > >>> 4.        Ch4. Q1 Source.
> > >
> > > Sorry, that looks like a cut and paste error, here is the link to the
> > > scope picture
> > >
> > > .png
> > >
> > > I used a 100ms timebase for the capture and then "zoomed in" a bit
> >
> >
> > You would need to zoom in far more to see what's going on when the SCR
> > triggers, to cover just a few cycles around the trigger time.
> >
> > Once an SCR has been triggerred, the gate becomes a voltage/current
> supply, a
> > diode drop above 0.
> > You see this on your trace in that after triggerring the gate sits at
> something +V
> > above 0.
> > The spike you see may just be an artifact of the internal SCR trigger
> action.
> > I presume you see some increased current draw from your bench supply for
> the
> > 3842 after the SCR triggers.
> >
> > What's up with channel 2? Above you say it's D19 anode which is 3842 Vcc
> but
> > it shows on the trace as just noise around 0V.
> >
> > I would still suggest that you scope the state of the secondary-side
> crowbar -
> > the gate of Q2, and base of Q4.
> > Should be simple to do, before trying to remove or disconnect the main
> > transformer.
> Oh dear! After Brent's question about D19 anode, I realise that the probe
> was connected to the cathode! I have now done it again with the probe
> connected to the anode. I have taken two images of the same capture, one at
> low resolution to show the overall behaviour
> And one zoomed in to show what happens when the SCR shuts down.
> png
> <>
> The channels are the same as before, namely:
> Ch1. 555 timer.
> Ch2. D19 Anode (now corrected as it was previously the cathode!)
> Ch3. D19 Gate.
> Ch4. Q1 Source.
> I got an earlier trace which showed the D19 anode at 9V, which is under the
> Undervoltage Lockout threshold, but I have not been able to repeat it.
> I don't fully understand the debate about using the variac.

I am not going to debate this either since I know what I have been doing
for years and it works perfectly well for me. I have fixed the bigger PSUs
in a VAX 11/750 (one broken switch transistor and multiple broken output
rectifiers). PSU in NORD-10/S (most carbon composition resistors had gone
out of spec). PSUs in many smaller machines as well.

I prefer to work in circuits where I can fiddle around without the danger
of getting killed all the time. Regardless of use of HV differential probe
it can be dangerous. Running it on 50VAC with a protection transformer do
expose a lot of problems already and you can poke around safely in the PSU.
I have not yet seen a problem that wasn't seen at low voltage, but I expect
there could be semiconductors that experience breakdown that occur at lower
than specified voltage.

> However, my
> measurements appear to suggest that when I use the variac the SCR triggers
> because of what appears to be a genuine overcurrent detected by R13. I
> think
> this is because the duty cycle at low AC input voltages is 50% (rather than
> about 10% or less as per the trace I have just taken), and I measured 2V
> across R13, which does seem to be enough to trigger the SCR. When I use
> 220VAC, the voltage across R13 does rise to 6V, which should also trigger
> the SCR I think, except that the peak last a lot less and so perhaps the
> fact that the 6V last for a brief period is insufficient to trigger it?

On the issue of duty cycle. If we look at this from the start up
perspective rather than the steady state perspective. At startup there are
no stored energy in the output filter capacitors. The voltage on the output
is thus 0. As soon as the PSU is doing its first switching pulse energy is
transfered as the main switch transistor is cutting off. The energy is
transfered into the capacitor and into the load. The voltage is starting to

The duty cycle generated by the PWM circuitry is in pure relation to the
voltage error, i.e. the difference between output voltage and reference
voltage. In essence it is a P-regulator.

When there are 0 Volt out the duty cycle will be at the maximum. Nothing
strange about that. But what is maximum duty cycle? It depends on the
circuitry used. The UC3842 can do up to almost 100% duty cycle. However it
may be wise to limit duty cycle in a flyback design so that the transformer
is not saturated. I am not sure if there is some kind of duty cycle
limitation in this circuit though.

So if it can handle 50% duty cycle at startup it should be able to handle
it at any time. Besides it would be incredible weird to design a circuit to
use a 10% duty cycle at its standard operating point and detecting over
current at 50%. Then you have much less head room for load and input

I am more or less convinced that what you see on the primary side is a
result of some kind of fault on the secondary side.
A very common problem is short-circuit rectifier diodes on the secondary
side (D12, D11, D21, D22, D23, D24). They can be difficult to measure
correctly in circuit since the resistance of the secondaries of the
transformer is so low. Depending on type you can either desolder them
completely or just lift one end of them.

My experience is that electrolytic capacitors seldom short circuit. They
probably boil and explode instead. Tantalum capacitors often short circuit.
Some of them goes into fire other just stay short circuit. So check for
tantalum capacitors and try to measure them for short circuit.

You have a crowbar on the secondary side. Are you sure that one hasn't
triggered? If you still run on variac you can disable the crowbar circuit
by removing the SCR and ramp up the voltage slowly to see if that makes any

Breaking the feed back loop:

R23 seems to be in the feedback path. If you lift it and insert a voltage
from a lab supply here you could simulate the output voltage and study the
behaviour of the UC3842 for different feed back voltages. You will see that
it will stay on max duty cycle up until close to the nominal voltage and
over a very small span change to almost no pulse out at all. This is due to
the gain of the circuit.


> I have seen the suggestions to study the waveforms at a much higher
> resolution. What I am doing is setting the overall timebase in the 100ms
> range so that I can trigger on when the 555 starts to oscillate and capture
> the whole period of operation until the SCR triggers. I can then zoom in,
> as
> can be seen from the trace provided in this email. I hope that is good
> enough, or am I missing some problem with doing it this way?
> I would like to follow Mattis's suggestions (and other people have said it
> too) to break the feedback loop, but it does look difficult to know how
> best
> to do it.
> I also understand Brent's suggestion that the gate spike is just the result
> of the SCR triggering, rather then the cause of the trigger. I had wondered
> if that might be the case.
> Regards
> Rob

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