QSIC update

Noel Chiappa jnc at mercury.lcs.mit.edu
Mon Feb 15 07:05:53 CST 2016

So here's a quick update on where Dave Bridgham and I are with the QSIC, since
I think we have reached a significant milestone.

We have the first of two wire-wrap prototype QBUS motherboards more or less
(see below) done, and working to do slave cycles on the QBUS. (I.e. we
implemented a simple register, and can write it, and read the contents back.)
A test program to write all 2^16 possible values, and read them back and check
them, ran several thousand complete passes with no errors.

To get there, we (Dave, really - he bore the brunt of the work on this
problem, and finally conquered it) had to tackle and fix some major noise
issues: the way the prototype is done (a wirewrap QBUS mother-board with bus
transceivers, level converters, etc, connected to an FPGA prototyping card
with flat cables), we think we had cross-talk problems in the cables (since
the connector pinout on the FPGA card, which we can't change, didn't alternate
ground and signal lines).

Anyway, it's working now; that means the hardware is 'mostly' working; most of
the work from here on out will be FPGA, etc, programming. There _are_ a few
additional QBUS lines used for bus master (DMA) and interrupts which we
haven't used yet, and one of the first things done now is to get those two
kind of bus cycles working; a) we have to get them done anyway, and b) that
will verify that the QBUS interface hardware is full working.

With that in hand, we can do the first controller (RK11), using memory in the
FPGA to simulate a small disk. We'll then try and get to the larger RAM on the
FPGA, to do full-size RAM disks. Next up after that is probably to hook up
some SD cards (we already have produced the small PCB daughter-cards, which
will mount on sockets on the wire-wrap mother-board, to hold the SD cards - we
still need to add those sockets and wire them up, hence the comment that the
wire-wrap mother-boards are "almost done"), at which point we'll have a
fully-functional prototype.

Dave has also produced prototype PCB's for the indicator panel, and one has
been stuffed, and Dave's about to try and hook that up, and get it running;
that will require yet a bit more work on the mother-board (install 3 sockets
to hold the driver chips for the signal lines in the interface to the
indicator panel). Blinkenlitz are a priority because, i) just because ;-), and
ii) being able to display data from inside the FPGA will be a big debugging

Anyway, we think getting slave cycles working was a major milestone (for a
couple of software guys :-), And we think (_hope_ :-) that progress will now
be pretty rapid, so hopefully more soon.


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