PDP 11/24 - A Step Backwards
robert.jarratt at ntlworld.com
Thu Mar 31 16:14:55 CDT 2022
I made some interesting discoveries this evening. See below.
> -----Original Message-----
> From: cctalk <cctalk-bounces at classiccmp.org> On Behalf Of Brent Hilpert
> Sent: 31 March 2022 21:03
> To: General Discussion: On-Topic and Off-Topic Posts
> <cctalk at classiccmp.org>
> Subject: Re: PDP 11/24 - A Step Backwards
> On 2022-Mar-31, at 12:36 AM, Noel Chiappa via cctalk wrote:
> >> From: Tony Duell
> >> A short in FET Q15 on the bias/interface board in the PSU could do it.
> >> The gate of that FET is driven from an LM339 comparator the -ve
> >> supply of which is -15V.
> > Ah; I hadn't even looked at the P/S prints.
> > (Like I said, I'm really weak on analog: for digital, I have the
> > advantages that i) although I'm basically/mostly a software person,
> > the MIT CS department is part of the EE department, and they made sure
> > that all the CS people had a decent grounding in the fundamentals of
> > digital hardware; and
> > ii) in my early years, I was involved in a number of actual hardware
> > projects, including a UNIBUS DMA network interface that tuned into an
> > actual product. So I'm pretty good with a digital circuit diagram,
> > like these CPU prints. But analog stuff is still a mostly-closed book
> > to me! :-)
> > Anyway, I'm happy to let you provide the analysis of the P/S... :-)
> >> From: Rob Jarratt
> >> [Perhaps] something else on the CPU caused Q15 to fail (if indeed it
> >> did).
> > I'd guess 'unlikely' (if Q15 has failed); UNIBUS ACLO is connected, on
> > the CPU card, to only a single gate (on K2), and that 383 ohm pull-up
> > (on K3), and the 1K pF cap there (the purpose of which I still don't
> > understand, unless it's just a smoother). Although I suppose that if
> > that cap failed, shorted, maybe that could have taken out Q15 somehow.
> Note: It's Q14 that controls ACLO, not Q15, Q15 is involved in the +5
> Unless there are two versions of the schematic and I'm looking at a
> one than everyone else.
> pdfPg.30 of
Thanks for pointing that out, I had not noticed the other line going down to
Q13 and Q14.
> >> Perhaps I should ... and disconnect ACLO, DCLO and LTC, they are all
> >> on the same connector
> > Now why didn't I think of just un-plugging that whole connector!
> > Duhhhh! My only concern would be leaving inputs floating...
> > DCLO, no problem; it has that pull-up on K3. (Ditto for ACLO, if the
> > buffering input gate isn't dead.) LTC, let's see... It's on K6, upper
> > left corner. I'm too lazy to work out what leaving that input floating
> > will do, and, if it has bad consequences, trace out all the places it
> > goes (it should be connected up to cause an interrupt, somewhere), but
> > there's no point; the KW11 has an 'interrupt enable' that has to be
> > set by software before it can do anything; so at the moment it's safe
> > to just ignore it for now, and stay with a focus on getting the main
> > CPU clock running. (LTC is not on the UNIBUS, so there's no pull-up on
> > the M9302 for it the way there is for ACLO & DCLO.)
> > So unplug that connector, and see if E70 (on K2, lower right corner) is
> > (Remember, the pull-up will give it an Ok input with BUS ACLO
> > disconnected.) If yes, great, go check the main CPU clock.
> Removing DCLO and ACLO from the PS to the bus may allow the CPU/clock to
> work. Or it may not.
Well I can tell you it didn't, disconnecting those connectors left the CPU
still not doing anything. However, there is a puzzle. On the CPU I found
that the track from the pull up resistor to E70 has been cut. This would
suggest that E70 pin 2 is floating, which I think means that K2 BUF ACLO H
is also floating (I haven't put a probe on it as yet). But as the cut is
deliberate, there must be a reason. The CPU did work for a while when I
first got the machine. K2 BUS ACLO L however has been patched to E52 pin 4,
which is the output of a gate on sheet K6. Can't say I understand why.
However, for whatever reason it would seem that perhaps the ACLO signal from
the PSU has always been considered bad?
> DCLO & ACLO behave as power-on-reset signals to the system. If they are
> allowed to just float up as the power supply comes up you have no
> guarantees as to the end result ('end' meaning the state of things after
> power supply has come up), without doing an analysis of the pertinent
> under their control.
> JFETs are being used as the ACLO/DCLO control devices for a reason. In
> contrast to bipolars, the normal/no-gate-voltage state of a JFET is
> Drain conducting, thus the initial state at power-up of ACLO-L & DCLO-L
> be 0V/low-impedance-to-GND. The point is to maintain that state until the
> power supply levels are good so the logic can be forced into a known
> Those three comparators in the H777 are looking at a time-delay ramp
Is that a typo? This is the H7140 not the H777.
> generated by C14 and the constant-current circuit of Q11.
> What is supposed to happen:
> - everything is initially 0V: V+5, ACLO, DCLO.
> - power is switched on. Internal voltage levels begin to rise.
> - after some delay, E4 trips first to start the +5 supply.
> - after some more delay, E5 trips, de-asserting DCLO (DCLO =
> - after some more delay, E6 trips, de-asserting ACLO (ACLO =
> The delays are presumably of some order of mS.
> -15V is the expected level from the E6 comparator output if AC is good. A
> Gate-Drain short in Q14 would be allowing that out to the bus. JFETs can
> flaky, a failed JFET wouldn't be a big surprise.
> So E6.6 = Q14.G = -15V is expected after power-up but an additional
> would be that a G-D short allowed excessive current from the bus through
> the E6 comparator output and damaged E6, or if left on too long burned out
> pull-up resistors on the CPU or bus terminator. However the LM301 is
> supposed to have current limiting so those things may not have been
I am a bit confused here. E6 is an opto-coupled isolator. Do you mean E9? It
doesn't look to me like Q14 is connected to anything that outputs -15V, but
Q15 is. A short in Q15 would surely be more plausible as the reason for -15V
> The scope could be used to observe what is going on with the +5, DCLO,
> ACLO sequencing at power up (with bus pull-ups, but without CPU).
> Removing only the ACLO PS-to-bus connection would allow DCLO to still
> exercise it's proper POR control. Once bus-ACLO is disconnected from the
> look for the clock LED after powering up with both bus-ACLO open (pulled
> high by bus & CPU) and bus-ACLO connected to GND. Manually
> connecting/disconnecting bus-ACLO to GND after power-up will trigger the
> CPU power-fail shutdown and disable the clock.
Given that ACLO is not actually connected to E70 and DCLO seems to be
operating correctly, I would think that disconnecting the connector is not
likely to help in this case.
I suspect I am going to have to check for shorts on the backplane and probe
the CPU module when it is powered.
More information about the cctech