PDP 11/24 - A Step Backwards

[Noel Chiappa]

    > does [disabling the MCLK counter via DCLO, asserted by the two
    > E126 monostable chain from ACLO] happen just on power-down, or on
    > power-up too? I'd need to understand how that two monostable chain
    > works in both cases, which I currently don't. (I only understand
    > monostables when pulses trigger them, not edges, which is a big part of
    > why I don't completely understand it.)

So this was bugging me, so I hauled out my TI TTL databook and looked up the
LS123.

According to that, the 123 is triggered by the rising edge on the B
(non-inverted) input, when the A (inverted) input is low (which it will be
here; it's tied to ground). (Also by the falling edge on A when B is high,
which we can ignore.)

So I think that chain is probably triggered only on power-down, which will
produce a rising edge on P FAIL. (Power-up will produce only a falling edge
on P FAIL, once power is up and good.)

(Note that the second monostable is triggered, also on B, by the -Q output of
the first; i.e. by the 'falling' edge of the first's pulse. But see also at
the bottom, below.)

So that should happen (if I have correctly understood this, which is not
certain, I'm just a software person :-) is that some time after P FAIL goes
high - a delay set by the first 123 - the second 123 produces a pulse (of a
width set by its RC pair) - which via E52 produces an assertion pulse on DCLO.

WTF? (Not that we care in this machine's case, since i) it only happens on
power-down, and ii) it's just a pulse, so it's affect on MCLK will be very
transient; it can't cause it to stay off. My curiousity has been piqued, is
all. :-) The TM does not, after a _thorough_ search (although there are a few
mentions of power u/down, but not this), explin why, alas. (The TM for some
_other_ -11 CPU, one which contains a similar circuit might, but I'm not
_that_ curious! :-)

My _guess_ is that the intent is to reset all devices to a good idle state,
_before_ power actually goes out. (Don't ask me why it just doesn't use
INIT, though!)


The potential fly in the ointment of complete understanding is that a 123 can
_also_ produce a pulse on a rising edge at the clear input - and there is
some circuitry driving the clear input on the second 123. (The clear input on
the _first_ 123 seems to be left hanging in space - odd!) It seems to be set
off by the mysterious DGP03 signal, generated by the microcode - but the GP
table on pg. 4-21 of the TM doesn't contain an entry for '3'? Unless it has a
typo - there are two '5' entries. In which case it could be 'Toggle the HALT
flip-flop (K6)' (which I don't see on K6, unless it's E78) but yah, pulsing
DCLO will probably clear it, wherever it is!


This machine is making my head hurt.

Disconnect the bad ACLO, power it on, and see if the CLK LED comes on. if not,
then we'll have to work out why not.

	Noel